ADC128S102QML-SP: ADC128S102QML

Rajan Bedi

Part Number: ADC128S102QML-SP

Hello,

For the ADC128S102QML, can you confirm that an external sampling clock is not required? How is the sampling frequency set between 50 kSPS and 1 MSPS?

Thank you

over 3 years ago

0 Collin Wells over 3 years ago

TI__Guru 63885 points

The ADC128S102QML-SP product does not require a free-running clock for operation. The ADC acquisition and conversion timing which determine the sampling rate are all based on the SPI interface timing. High frequency (16MHz) SCLK signals result in the full 1MSPS sampling rates and a slower (50kSPS*16clks/sample) = 800kHz SCLK would result in the 50kHz sampling rates. The first 3xSCLKs define the Track/Acquisition period and the remaining clocks are used for the conversion/hold phases.

0 Rajan Bedi over 3 years ago

Expert 1565 points

Thank you very much Colin, what CAD data exists for this part, e.g. schematic symbol, PCB footprint, 3D step model?

0 Collin Wells over 3 years ago in reply to Rajan Bedi

TI__Guru 63885 points

Hello,
We offer this information on the device product folder in the Design & development section. I copied it below for easy reference.
For additional terms or required resources, click any title below to view the detail page where available.

Package	Pins	Download
(Y)	0	View options
CFP (NAC)	16	View options
CFP (NAD)	16	View options

0 Rajan Bedi over 3 years ago in reply to Collin Wells

Expert 1565 points

Hello, The CAD data for the NAC package does not work, can you check what has been uploaded to Ultra Librarian please.

Kind Regards,

Rajan

0 Collin Wells over 3 years ago in reply to Rajan Bedi

TI__Guru 63885 points

Hello Rajan,

I have submitted a ticket with the owners of that tool to look into the situation. Would you confirm the error/challenge you experienced along with the CAD tool you were using to view the information?

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ADC128S102QML-SP: ADC128S102QML