ADS54J60EVM: SAMPLING MAPPING FOR LMFS_8224

Mani,

What reference clock is used by the FPGA? Is the LMK setting correct for this clock? What FPGA are you using?

If you go to the TSW14J10EVM product folder on the TI website, you can download example firmware that Xilinx created for TI to use with TI ADC's and certain Xilinx development boards. This may help you.

Please see attached example reference design which is using this ADC with a Xilinx FPGA, which is based off of  TI based JESD204B IP, that is free to customers. To apply for this IP, just go to the following link:

https://www.ti.com/tool/TI-JESD204-IP

Regards,

Jim

hi jim,

i am loading the default configuration which are available are in the ads54j60evm GUI. i am following the same steps as in ads54j60evm user guide and the same file as used in it.

The GUI is assuming a connection to an Altera FPGA which is used on the TI data capture card (TSW14J56EVM). The firmware used by this board may use a different frequency for the FPGA reference clock than what your firmware requires. That is why I asked the questions I did so I can help you verify if the LMK is set properly.

Hi jim ,

thanks for the early reply.

fpga clock is 245.76MHz and clock to ADC is 983.4 MHz,SYSREF  is 3.84MHz

LMFS IS 8224, K =16

The GUI settings should be fine.

Any chance the FPGA has scrambler enabled? The ADC does not.

Hiee jim

no scrambled is not enabled. Does my transport layer logic is correct. I hav sent the file already to u.

I have no idea. I am not a FPGA expert. Any chance Xilinx can assist with this? Most of our firmware development was outsourced. I will check with our current firmware designer, but a response may be delayed.

Looking at your transport layer, it does not appear correct. I cannot make sense out of it with respect to the data pattern shown on page 41. Also, the data lanes between the FMC and ADC are not routed 1:1 with respect to the standard. Not sure if you caught this or not. For instance, JESD standard data pair DP0_M2C_P/N on FMC pins C6/C7 route to DB1 of the ADC. 

Hi jim,

that would be a great help.

FYI i was using the same transport layer code which was given in ads32rf45evm firmware for 8224 designed by TI .it is in your website with KCU105 board because ADC output connection to FMC is same for both EVMs and my fpga connection are similar to KCU board. 

only channels are swapped wrt ADS32rf45 evm.

Not sure what your last comment means since both boards have the same mapping.

Try sending a lower input frequency tone, or use a saw tooth input to simulate a ramp. This helps sometimes with trying to un scramble the data.

Can you try using a different LMFS modes like 4211, or 222 or 124? This may help trouble shoot this issue as well.