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ADS1282-SP: Power-on sequence

Daniele Lippi
Prodigy 150 points
Part Number: ADS1282-SP
Other Parts Discussed in Thread: ADS1282

Dear all,

I have some question about Power-ON Sequence.

ADS1282-SP has 3 power supplies: AVDD, AVSS and DVDD.

Datasheet says that there is no specific order applicable to device power supplies; then it says that internal reset is removed when AVDD-AVSS and DVDD exceed 3.5V and 1V, respectively.

Somewhere else is written that SPI could start improperly and require a dedicated reset procedure to make the device correctly reading SCLK.

I would like to have confirmed that I can cycle AVDD-AVSS without removing DVDD without damaging or improperly starting the device.

Thank you in advance.

Daniele

  • +1
    TI__Mastermind 44680 points

    Hi Daniele,

    You should be able to power cycle AVDD/AVSS without having to turn off DVDD. The only thing I would consider would be the state of the analog input pins when cycling the analog supply...

    Internally, the analog inputs are connected to AVDD/AVSS through ESD diodes. If the analog inputs are being driven while the analog supplies are tri-stated, then AVDD may be back-driven and float up to approximately VIN - 0.4 V (a typical diode drop). So long as there are no other sources or contentions on AVDD this behavior will be harmless. However, if circuit conditions result in the ESD diodes continuously sourcing/sinking more than 10 mA (per datasheet Abs. Max ratings) then there would be some cause for concern that the could be device could be damaged depending on how long it is in this state.

    For proper SPI communication, the datasheet does recommend resetting the device (or at least the serial interface) in case of glitches on the SCLK signal that would result in the SPI peripheral and controller getting out of sync (i.e. the ADC interprets a glitch on SCLK as a clock pulse and is then 1 clock period ahead of the controller). This is intended as a precaution since there is no "/CS" signal on the ADS1282 to reset the serial interface and during power-up the SCLK signal might be floating. However, with DVDD powered and a stable (driven) SCLK signal applied I don't think you will have any SPI communications issues after power-cycling AVDD/AVSS.

    Best regards,
    Chris

  • +1 in reply to Christopher Hall
    Prodigy 150 points

    Dear Christopher,

    Christopher Hall said:
    For proper SPI communication, the datasheet does recommend resetting the device (or at least the serial interface) in case of glitches on the SCLK signal that would result in the SPI peripheral and controller getting out of sync (i.e. the ADC interprets a glitch on SCLK as a clock pulse and is then 1 clock period ahead of the controller). This is intended as a precaution since there is no "/CS" signal on the ADS1282 to reset the serial interface and during power-up the SCLK signal might be floating. However, with DVDD powered and a stable (driven) SCLK signal applied I don't think you will have any SPI communications issues after power-cycling AVDD/AVSS.

    I'll have the ADC AVDD/AVSS power supply cycled by the FPGA, thus SCLK will be driven to GND during AVDD/AVSS power cycling.

    Christopher Hall said:

    You should be able to power cycle AVDD/AVSS without having to turn off DVDD. The only thing I would consider would be the state of the analog input pins when cycling the analog supply...

    Internally, the analog inputs are connected to AVDD/AVSS through ESD diodes. If the analog inputs are being driven while the analog supplies are tri-stated, then AVDD may be back-driven and float up to approximately VIN - 0.4 V (a typical diode drop). So long as there are no other sources or contentions on AVDD this behavior will be harmless. However, if circuit conditions result in the ESD diodes continuously sourcing/sinking more than 10 mA (per datasheet Abs. Max ratings) then there would be some cause for concern that the could be device could be damaged depending on how long it is in this state.

    Here above, you can see an excerpt of my electrical schematic.

    Electrical Data:

    • AVDD/AVSS = +5V / 0V
    • VREFP/VREFN = +5V / 0V
    • AVDD/AVSS and VREFP/VREFN are provided by the same high precision source
    • ANP1/ANN1 are fed through 1kohms resistors by an amplifying, then differentiating chain
    • ANP1 will nominally range from 1V to 3.5V on  (typo on the schematic)
    • ANN1 will be fixed to 1V, provided by the OPA on the picture's top-left
    • Protection diodes were provided to prevent ADC's modulator from damage in case the differential input should exceed modulator's dynamic (in this case 2.5V) or either pin exceed the admitted voltage swing, i.e. AVDD-1.25V = 3.75V or stay below AVSS+0.75V = 0.75V

    My understanding is that in the worst normal case on each input pin would flow no more than 5mA, thus the possible problem you pointed out should never occur, should it?

    Best regards,

    Daniele

  • +1 in reply to Daniele Lippi
    TI__Mastermind 44680 points

    Hi Daniele,

    Correct. I usually disregard the internal ESD diode drop to provide some extra margin and to simplify the input current calculation, so you're looking at less than 3.5 mA (e.g. 3.5V / 1kOhm) under normal operating conditions (ignoring the external protection diodes...depending on the forward voltage drop of those diodes, they may not steer much current away from the device when AVDD/AVSS is powered down if their forward drop is larger than the internal ESD diode forward drop).

    Best regards,
    Chris