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ADS8168EVM-PDK: Are READY and ALERT signals synchronized to SPI clock?

Hsinru Chiang
Prodigy 10 points
Part Number: ADS8168EVM-PDK
Other Parts Discussed in Thread: ADS8168

Hi,

I know READY and ALERT are digital output.

Because there is no other digital clock input from outside of the chip, all digital outputs will be synchronized with SCLK.

Am I correct?

If not, what clock frequency are READY and ALERT operated at?

I know it is a weird question but I am now designing GPIO block in FPGA. So I want to confirm which clock frequency and domain I should use in my design.

Thanks.

  • +1
    TI__Expert 3785 points

    Hi Hsinru,

    The READY and ALERT signals are driven with the clock from internal oscillator of the ADS8168. The READY and ALERT signals indicate events that happen only once per conversion result. Hence the maximum switching rate of the READY and ALERT signals will be equal to the sampling rate i.e. CSz frequency.

    One of the approaches would be to synchronize the READY and ALERT signals with one of the FPGA's clocks by detecting rising-edge or falling-edge for the READY and ALERT signals with a clock that is 4x faster than CSz.

    Regards,

    Rahul