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ADC12DJ2700: Timestamp

Part Number: ADC12DJ2700

Team, 

We would like to use the timestamp functionality on the ADC. See the snippet of the datasheet below.

It is unclear to me whether the TMSTP implements a LVPECL and LVDS receiver for this differential pair.

The signals to these inputs are LVPECL signals.

I would like to know if I can implement a DC-coupled solution assuming the chain is LVPECL driver to LVPECL receiver. (See SLLA120 snippet below)

If TMSTP is a LVDS receiver, I would then need to translate my LVPECL signal into LVDS and then use an AC coupling scheme. (See SLAA840 snippet below)
Chain: LVPECL driver >> LVDS Translation >> LVDS receiver

  • Hi Michael, 

    The TIMESTAMP signal is a differential signal but it does not exactly match the voltage swing and common mode standard for LVPECL or LVDS. Here are the signal swing requirements for TIMESTAMP signal 

    Here is how you could DC couple the TMSTP signal from FPGA. 

    The FPGA has internal 50ohms resistors and the ADC also has 50 Ohms to ground for each leg when TMSTP_LVPECL_EN = 1. So in theory the circuit shown below should work and there shouldn’t  be a need to add any component . 

    Regards,

    Neeraj