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DAC37J84EVM: Xilinx eval boards match for DAC3XJ8XEVM

Part Number: DAC37J84EVM
Other Parts Discussed in Thread: ADS54J40EVM, , TSW14J57EVM


We are looking at connecting the DAC3XJ8XEVM reference design board to a Xilinx UltraScale+ evaluation board - KCU106 or ZCU102 for example. 

So far I can see some pin mapping discrepancies and in connection to this I have a couple of questions:

1. Is there a list of FPGA evaluation boards (from Xilinx or Intel) that can work with DAC3XJ8XEVM?

2. What evaluation board was originally used for the DAC3XJ8XEVM development?


  • Dessislav,

    The same answer I sent regarding the ADS54J40EVM also applies to the DAC3xJ8xEVM. The only difference is the Zynq platforms did not route the SYNC+/- pins to the correct FMC pins per the Vita-FMC standard. To use these platforms with the DAC EVM, you must connect SYNC to a spare SMA on the Zync board that routes to spare FPGA pins  and connect it to J21 pin 1 (CMOS_SYNC_AB) on the DAC EVM.



  • Thank you for the clarification, I'm planning to use ZCU102 which should fine according to your previous response. 

    For completeness I'm adding your previous response here, assuming same applies to DAC37J84EVM. 


    The ADS54J40EVM can work with the Xilinx development kits shown below. The EVM also works with the TI TSW14J56EVM (Arria V FPGA) and TSW14J57EVM (Arria 10 FPGA). The TSW14J56EVM  board was used with the initial development. 



    Development Kit

    Kintex UltraScale KCU105            

    Kintex-7 KC705                                 

    Virtex-7 VC707                                 

    Virtex UltraScale VCU118             

    Zynq UltraScale ZCU106                

    Zynq-7000 SoC  ZC706                   

    Zynq UltraScale ZCU102                

    Artix AC701    

  • Thank you for the clarification about the SYNCp/n signal and the extra SMA jumper cables connection required. I was looking at it and the SYNCp/n signal is an output of the DAC (seems wrongly shown on the schematic as an input, datasheet shows it's and output and it is "Synchronization request to transmitter, LVDS positive output. It can be left open if not used"). Currently I'm not planning to use the SYSREF signal and because of that I think I don't need the SYNC signal as well. Please correct me if I'm missing something here.

    Also I have a similar additional question about this board, related to its AC coupled output. I need the output to be DC coupled and the way to implement it is by shorting T1 pins 3&4 and 6&1 and on T2 pins 1&6 and 3&4, see picture below.

    Do you see any issues with this conversion of the output from AC to DC coupling?

  • Dessisiav,

    When using JESD204B devices, SYNC is always required. This part can drive SYNC either as6813.JESD204B Overview - May 2018.pptx differential LVDS or single-ended CMOS. It appears you are new at using JESD parts. I have attached a JESD204B training overview that may help you. The DAC will require the SYSREF input as this is needed to synchronize the internal clocks. 

    You can convert the board to DC coupling by removing the transformers and shorting the pads with 0 Ohm resistors to make a connection to the SMA connectors.



  • Thank you for the quick answer with the clarification and the link on to how to use JESD IF.

    This answers my questions.