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Original question:

DAC3154: Data Input Alignment

DAC3154: SPI write causes halt to operation

David Wende
Intellectual 620 points
Part Number: DAC3154

I am trying to write both default and non-default values to some registers (specifically 0x44E4 to config0 or some clkdelay values to config3).

It seems that any write to these registers halts operation of the DAC (as viewed from the current output pins).

 Even a single write of 0x0 to config3, which is the default value, has the same effect.

The SPI is being operated at about 2MHz and timing on it seems OK.

Any ideas would be appreciated.

David

  • 0
    TI__Guru* 91947 points

    David,

    How are you getting an output if the SPI is not working properly? Can you write to a register then read back the correct value? Are you using 3-wire or 4-wire SPI? The default is 3-wire SPI. To use 4 wire, you will need to set bit 9 of Config0.

    What level are input pins VFUSE, Sleep, Txenable, and ResetB set to?

    Make sure the SPI signals are following the protocol shown in Figures 49 and 50 of the data sheet. These signals levels should be per the table in sheet 12 of the data sheet.

    If you can do writes and reads, verify the current drawn by the part is reduced when putting DAC A & B to sleep by writing 0x0060 to Config10.

    Regards,

    Jim   

  • 0 in reply to jim s
    Intellectual 620 points

    Hi Jim

    Thanks for your reply. I will only be back in the lab on Sunday when I will try and record the information you suggested.

    In the meantime note:

    1. I did not mean that SPI ceases working, I meant that the DAC outputs stop. Maybe also the SPI ceases but I have no indication of this.

    2. I never changed to 4 wire SPI so I guess I am using 3 wire. However, my present setup does not allow me to read back over SPI (bugs in FPGA design).

    But I could also just do a SPI read and decipher the answer from the scope waveform.

    3. In any case I will send you scope screen shots next week.

    Thanks again

  • 0 in reply to David Wende
    TI__Guru* 91947 points

    David,

    Please send your schematic if you would like me to take a look at it.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 620 points

    Hi Jim,

    I had SDO and SDIO swapped.

    I fixed that problem and also added read function to SPI.

    R/W SPI now works OK and it seems like DAC is functioning OK also.

    Attached schematics I would nevertheless appreciate critical review, maybe I could improve the performance.

    Thanks a lot

    0317.dac.pdf

    0317.dac.pdfdac_amp.pdf

  • 0 in reply to David Wende
    TI__Guru* 91947 points

    David,

    1. To get more current out of the device, add a 6.98 Ohm series resistor to the R28.
    2. You should isolate all of the supplies with ferrite beads and capacitors. See attached schematic.
    3. The DACCLKP/N should come from a clean source, not an FPGA which is what I think you are showing. If this is your only option, I would suggest adding as 1:2 buffer to remove the daisy chain connection you currently have. If running the clock at 500MHz, this could have some serious reflection issues.
    4. The supply voltage used to tie ALIGNP high should be the same supply used for the DIGVDD18 power inputs.
    5. The TI EVM uses 49.9 Ohm resistors to GND on the DAC output. I would suggest sending this schematic to the high speed amplifier forum for their comments about the amplifier interface. See attached document for more info regarding this.

    Regards,

    Jim

     2352.DAC31X4EVM_B-SCH.pdfpassive termination.pdf1157.DAC to Op Amp Part 2, Current-sourcing DACs slyt360.pdf2045.DAC to Op Amp Part 3, Current-sourcing DACs slyt368.pdf

  • 0 in reply to jim s
    Intellectual 620 points

    Thanks Jim,

    1. Is there any info on relationship between resistor at BIASJ and full scale current?

    2. Yes - that would have been a good idea

    3. We will run at 200MHz max. Yes, clock is coming from FPGA (direct from internal PLL) but in my application a bit of jitter is not critical. The placement of the LVDS to LVPECL is quite good (on layout) so I don't expect too many problems from this. I actually had no more pins left on the FPGA for a separate clock output.

    4. Next spin of the board. After your comment I noticed that I am exceeding maximum ratings on this pin (2.5V). I hope the device lasts until I can do another board :-)

    5. Yes will change to 49.9 and also post on forum in a few days.

    Thanks for the helpful feedback.

    David

  • 0 in reply to David Wende
    TI__Guru* 91947 points

    David,

    Iout full scale current = 16 x Ibias = 16 x (Vextio/Rbias) = 16 x (1.2V/960) = 20mA.

    Regards,

    Jim