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DAC37J82: dac37j82 - Cannot establish a link

Guy Bilibau1
Prodigy 30 points
Part Number: DAC37J82


Hi

We try to establish link between FPGA (xilinx) and dac37j82

The parameters are:

Dac clock : 480MHz

Sysref : 15MHz

L : 4

M : 2

F : 1

S : 1

K : 32

Serdes bps : 4.8GHz

HD : 1

Nco : 140MHz

Dac pll : off

 

We initialize the registers using the GUI

But we can’t establish a link (SERDES PLL is locked)

what could be the problem? 

we are having a hard time understanding the connection between the SERDES lane and the JESD ID configuration, if i mux the SERDES using Reg 0x5F, 0x60 does 0x46, 0x47, 0x48 needs to change accordingly?

Appreciate your kind help.

Thank you

  • 0
    TI__Guru* 91947 points

    Guy,

    Please check your register settings against the file attached. This file is working with your setup on our hardware. What clock frequency is your FPGA expecting?

    If you are muxing the serdes data, the lane ID must also be set properly (0x46, 0x47, 0x48).  

    Regards,

    Jim 

    421_K_32_Fs_480M_NCO_140M.cfg

  • 0 in reply to jim s
    Prodigy 30 points

    Hi Jim,

    Thanks for the answer! Fixing the JESD ID and SERDES mux's fixed my issue.

    another thing i see which i don't understand.

    Register 0x51:

    when it is set to 0xff -> 0x64.. indicates for a link configuration error, and no output from the DAC.

    when 0x51 is set to 0x00 -> No errors and Output is good, going back to 0xff doesn't bring down the link, output is still good.

    in your configuration you sent you write to 0x51= 0x00DC, which ignore link configuration error.

    What should be set? i do want to use the sync request mechanism to overcome some link problems.

    Thanks,

    Guy

  • 0 in reply to Guy Bilibau1
    TI__Guru* 91947 points

    Guy,

    I am guessing the issue is a Link Configuration error. I would try setting 0x51 to 0xDD then 0xDE to verify there are no disparity or not-in-table code errors.

    I have seen in the past where a FPGA entry for an ILAS parameter is defined different than what the DAC uses. For instance, the K, M, S, L and F values are all entered as the value minus 1. If the FPGA uses the value as is (not subtracting 1), when the DAC sees that these values are not the same, it will report a link configuration error and send SYNC low. The CGS will repeat and the ILAS will fail again, and this will repeat forever. Did you notice SYNC toggling when you had 0x51 set to 0xFF? If this is the case, I am not sure this can be fixed as this would require the FPAG parameter to be set incorrectly to match the DAC value.  

    Regards,

    Jim