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ADS62P48: CMOS CLKOUT frequency limitation

Part Number: ADS62P48

Hi sir,

I have an old design (5 years) with ADS62P48 that was working fine at 100Msps with CMOS IQ bus.

Today i need to boost the sampling to 200Msps with minimum change in this design.

I test it in one card, changing the synthesizer frequency and all seem to work well.

CLKOUT pin has a small logic level, 1.2Vpp instead of 1.8Vpp...

As i read (note7 page11 in Data sheet) , there is a 150Msps limitation on CLKOUT in CMOS Mode...

Could you please explain in detail why there is this limitation?

For me a minor change is to place a fast buffer as close as possible to CLKOUT pin.

What is your feeling?



  • Hi Alain,

    I can check into the specifics as to why there is a 150Msps limitation on the CLKOUT in CMOS mode. You can try the buffer modification you suggested, but TI can only guarantee device performance based on the datasheet specifications.

    Regards, Amy

  • Hi Amy,

    Thanks for your quick answer.

    I just want to know if this limitation is because CLKOUT buffer is unable to drive capacitive load to frequency above 150MHz,

    so an external buffer save this design...

    But perhaps it is a problem of speed in the internal ClockGen circuits...

    Could you please give me more precisions?



  • Alain,

    First, it appears there is an error in the data sheet. In Table 3, Tstart MAX for 150MSPS should be 0.6 not 6. Then as the sampling frequency rises above 150Msps, it will be hard for a user to capture data with enough setup and hold time if using the OUTCLK as you can see the Tstart value really starts to increase as well as setup and hold times decreasing.  Also, the OUTCLK duty cycle is at 43% in this frequency range which could effect the setup and hold times.