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ADS131M06: Intermittent

Eddie Koh
Genius 10635 points
Part Number: ADS131M06


I'm using ADS131M06 ADC (with a STM32G474), and having issues setting the PGA gain 8x and above.

 

I have multiplexed all channels to the positive internal test signal, which I believe is designed to read the same ADC value irrespective of which PGA gain is in use. This is proving correct when we use 1x, 2x or 4x gain. However, when we use 8x or above, the ADC reads over 4 times higher than expected. Again, this is with the ADC test signal.

 

We're checking the CRC of each frame read back from the ADC, so I'm confident that the values are being received correctly. If we use the 1/2/4 gain settings, we have no other issues with the ADC - measurements are correct, and our product functions without issue.

 

Even when using internal test signals, this was observed. The behaviour is intermittent. Without changing the software at all, sometimes we read the correct ADC value for the test signal, and other times we read a value that's about 4 times higher than expected. Throughout these tests, channels set to 1x 2x or 4x, consistently read the test signal correctly.

Additional system level information:

We currently have an issue on our board where the 3V rail (used as AVDD for the ADS131M06) does not come up as cleanly as we want, but we can reproduce this ADC issue when supplying that rail from a bench PSU, and also when resetting our board (supply remains stable).

 

The CLKIN for the ADC is 8.192MHz, supplied from a timer on the STM32. We enable this clock in software, and then toggle the SYNC/RESET line for 2058 CLKIN cycles - to reset the ADS131M06. Then, we clock a response frame out of the ADC and verify that it matches the expected POR response (0xFF20 | CHANCNT), which it does. From this, I am assuming that the ADC has started successfully.

 

Is there anything different about the 8x and above PGA gain settings that we need to know about?

  • 0
    TI__Mastermind 18900 points

    Hello Eddie,

    These graphs are the big ones to pay attention to when switching gains from 1-4 to 8-64 (just click on them to make them unblurry, or take a look at the datasheet):

    To my knowledge, none of these should affect the internal test signal mode as they have everything to do with the PGA circuitry. I have heard of issues of the internal test signal failing to adjust to the correct value at the higher gains, as the signal needs to be smaller to attain the same output voltage. I will have to do some digging tomorrow and clarify this.

    But it doesn't sound like your communication interface, or backend code, is contributing to this issue. If you can communicate to the device, you can assume it started up correctly, i.e. the unstable rail wasn't bad enough to put the device into a weird state. A test to pinpoint the internal test signal mode would be to tie the inputs to ground, instead of the test signal, and seeing if the offset voltage at the inputs scales incorrectly as you see with the test signal (or correctly with the intended gain). 

    Thanks,

    -Cole

  • 0
    TI__Mastermind 18900 points

    Hello Eddie,

    Just to confirm, I couldn't find any inherent issues with internal test signal. Let me know the results of tying the inputs to GND to see if the gains scale as expected.

    Thanks,

    -Cole