ADS8924B: About SDO

tomohiro yamada

Prodigy 30 points

Part Number: ADS8924B

When is the input analog value fixed when the data is converted from analog to digital?

over 2 years ago

+1 Keith Nicholas over 2 years ago

TI__Mastermind 40610 points

Hello Yamada-san,

The analog input voltage is fixed (or held) at the end of the acquisition period. The end of acquisition is also the beginning of the conversion period, and occurs when the CONVST signal transitions from low to high. In other words, hold mode occurs when the MCU/FPGA takes CONVST high.

Regards,
Keith Nicholas
Precision ADC Applications

0 tomohiro yamada over 2 years ago in reply to Keith Nicholas

Prodigy 30 points

Hello Nicholas-san,

Thank you for your prompt response.
By reading the answers I received, I was able to understand.

I'm always grateful for your help.

Regards,
Tomohiro Yamada

0 Keith Nicholas over 2 years ago in reply to tomohiro yamada

TI__Mastermind 40610 points

You are welcome.

Keith

Data converters

Data converters forum

ADS8924B: About SDO