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TSW14J57EVM: error "Couldn't get the link up for RX"

May
Genius 9880 points
Part Number: TSW14J57EVM
Other Parts Discussed in Thread: TSW14J58EVM

Hi,

Customer have encounter error with this devices, please see details below.

"We have a devices connected to each other AFE79XX series and TSW14J57. When we run Latte setup program, we get an error "Couldn't get the link up for RX"
We don't know it is because of the button (SW1 reset and SW2 reset) we have pressed on the AFE79XX, because It has worked properly before that. 

Please refer to log text. 

#======
#Executing .. AFE79xx/bringup/setup.py
#Start Time 2022-02-15 20:08:09.268000 
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Purge
MPSSE mode set
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
#Done executing .. AFE79xx/bringup/setup.py
#End Time 2022-02-15 20:08:16.795000
#Execution Time = 7.52700018883 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE79xx/bringup/devInit.py
#Start Time 2022-02-15 20:08:23.953000 
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
#Done executing .. AFE79xx/bringup/devInit.py
#End Time 2022-02-15 20:09:10.857000
#Execution Time = 46.9040000439 s 
#================ ERRORS:1, WARNINGS:0 ================#
#======
#Executing .. AFE79xx/bringup/AFE79xx_EVM_Mode7.py
#Start Time 2022-02-15 20:09:30.249000 
TXA cannot be enabled when TXB is disabled. Consider enabling TXB instead of TXA.
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 14745.6
laneRateFb: 14745.6
laneRateTx: 14745.6
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 14745.6
laneRateFb: 14745.6
laneRateTx: 14745.6
Device Initialization for ChipVersion: 2.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x20
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
SPIA has got control of PLL pages
PLL Locked
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Sysref Read as expected
Waiting for MACRO_DONE bit to go high, Count: 1
Got MACRO_ERROR : EXECUTION_ERROR
MACRO_OPCODE : 0x13 MACRO_NAME : POWER_UP_CALIB
Macro Error Status Interpretation is Undefined in MacroLib
ERROR INTERPRETATION is : Not Interpreted
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0xff00
###################################
###########Device DAC JESD-RX 1 Link Status###########
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0x0
###################################
#Done executing .. AFE79xx/bringup/AFE79xx_EVM_Mode7.py
#End Time 2022-02-15 20:11:38.483000
#Execution Time = 128.233999968 s 
#================ ERRORS:23, WARNINGS:1 ================#
#======
#Executing .. AFE79xx/bringup/bringup.py
#Start Time 2022-02-15 20:14:10.114000 
The External Sysref Frequency should be an integer factor of: 3.84MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 14745.6
laneRateFb: 14745.6
laneRateTx: 14745.6
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 14745.6
laneRateFb: 14745.6
laneRateTx: 14745.6
Device Initialization for ChipVersion: 2.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x20
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
SPIA has got control of PLL pages
PLL Locked
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
SPIA has got control of PLL pages
PLL Pages SPI control relinquished.
Sysref Read as expected
###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
Serdes-FIFO error for lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 0; Alarms: 0xff00
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
LOS Indicator for (Serdes Loss of signal) lane 2: 1
LOS Indicator for (Serdes Loss of signal) lane 3: 1
Serdes-FIFO error for lane 3: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b10101010
FS State TX0: 0b00000000 . It is expected to be 0b01010101
Couldn't get the link up for device RX: 1; Alarms: 0xbf00
###################################
#Done executing .. AFE79xx/bringup/bringup.py
#End Time 2022-02-15 20:15:46.452000
#Execution Time = 96.3379998207 s 
#================ ERRORS:25, WARNINGS:1 ================#

Thank you in advance.

Regards,
Maynard

  • 0
    TI__Genius 17831 points

    Hi Maynard,

    SW1 is hardware reset signal for AFE. SW2 is reset signal for on-board CPLD. Pressing SW1 and SW2 before running the configuration script should not affect functionality of the EVM. The errors seen by the customer are not expected due to that.

    I see that when AFE79xx_EVM_Mode7 script is executed, there's some unexpected log "TXA cannot be enabled when TXB is disabled. Consider enabling TXB instead of TXA." It looks like script is updated from default. 

    Can you have them test with default script? If the customer has modified the script can they provide it for us to test on an EVM?

    Also, I see that the customer ran the bringup.py script. We do recommend using this script with their setup as this script was made for the TSW14J58EVM and does not support the TSW14J57.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    TI__Genius 9880 points

    Hi David,

    Just received response from customer, please see details below.

    " I have fixed the error with TX before hand. I wanted you to look at the later parts of the log file. Our main error is about RX. You can see that from the new log file that I am attaching. Because we checked that with using 2 different computers, and one of them had default scripts of Latte. However the problem (log) was almost exactly same. That is why I don't think the error has happened because of the script. On top that i have noticed that the RX LEDs are not on when trying to access the data from ADC page HSDC pro. I am also attaching the error window that HSDC pro is showing me when trying to run the processes. I would greatly appreciate if you could help me solve this issue.

    Lattelog (2).zip

    "

    Regards,
    Maynard

  • 0 in reply to May
    TI__Genius 17831 points

    Hi Maynard,

    The errors that the customer is seeing in the log are for the two DAC JESD links, DAC JESD Rx 0 and DAC JESD Rx 1. Before running the script are they setting up HSDC Pro to send a tone to the AFE? 

    I have created a document that shows how to use the AFE79xxEVM with the TSW14J57. Please have the customer follow this document and see if they can capture data in HSDC Pro.

    The document can be downloaded from this link: https://tidrive.ext.ti.com/u/omcyWTHnMnywZzJe/e2dfc9f4-0e08-4b66-a9fb-446feb3a266f?l 

    Regards,

    David Chaparro