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ADC128S102QML-SP: transmit SPI signal over long distance

Part Number: ADC128S102QML-SP

Hi,

In my application, I need to have processor communicate with ADC128 at some long distance. As distance is long, memory mapped ADC128 will not be useful.

Read the Analog Applications Journal Extending the SPI bus for long-distance communication by Thomas Kugelstadt. One of the possible solution for restoring synchronicity between the slave data and the interface clock is to feed the clock signal from the slave back to the master

I'd like to know is there any other method to solve the sync issue for ADC128 between the slave data and the interface clock if the clock feedback is not available?

Thanks for your attention.

  • Hello,

    The challenge you've mentioned is common to all SPI ADCs that are forced to operate over a long distance as it's really intended for inter-board and short-distance communications primarily.  The delays involved in longer distance communications eventually violate the setup/hold times of the digital communications with the ADC.  Here are a few suggestions.

    1.)  Operate the SPI bus at the lowest speed possible for your application.  Slower data rates will be more tolerant of the delays and signal-rounding that are common in longer-distance transmissions.

    2.) Utilize a buffered return clock that the MCU will use to latch the data.  This signal should be routed back out of the ADC connection with the ADC DOUT signal back to the MCU and ideally the two are relatively synchronized to each other and meet the setup/hold times

    3.) More advanced MCUs, and all FPGAs have the ability to internally delay when the incoming data is latched/sampled relative to the outgoing SCLK.  If the transmission distance is constant then characterizing a few setups would yield some typical values for the required delays.

    4.) Have a local MCU that communicates with the ADC and then transmit the data over a different interface meant for longer-distance transmission - e.g. RS-485 or RS-232.