Hello.
We use the ADS1292 for ECG with DC Lead-Off and the configuration "Input Current Source".
The problem is, we have a noise on both channels of about 35 Hz. Dry instead of wet electrodes are used on the inputs.
The power supply of the front end is provided by means of an LDO (LP8900TLE-3333/NOPB). The input of the LDO is powered by a lithium polymer battery with 880 mAh and a nominal voltage of 3.8 V.
We use digital filters with a range from 0.5 Hz to 40 Hz. We have also deactivated these on a test basis to see if 35 Hz is a side effect of our digital filtering. Unfortunately they are not.
Could the 35 Hz or so originate within the front end? The amplitute of the noise is 30 µV with good transition resistance and 1 mV with poor transition resistance. With the ECG simulator, the interference is not visible.
Thank you.
With kind regards
René Tauscher
Our schematic:
Sample for noise:
Our firmware configuartion:
//--- CONFIG1: Configuration Register 1
//--- This register configures each ADC channel sample rate
(0x00 << 7) + /*!< Bit 7 SINGLE_SHOT: Single-shot conversion
0 = Continuous conversion mode (default)
1 = Single-shot mode */
(0x00 << 3) + /*!< Bits[6:3] Must be set to '0' */
(0x03 << 0), /*!< Bits[2:0] DR[2:0]: Channel oversampling ratio
Attention! fCLK = 512 kHz and CLK_DIV = 0 or fCLK = 2.048 MHz and CLK_DIV = 1.
BIT OVERSAMPLING RATIO DATA RATE(1)
000 fMOD / 1024 125 SPS
001 fMOD / 512 250 SPS
010 fMOD / 256 500 SPS (default)
011 fMOD / 128 1 kSPS
100 fMOD / 64 2 kSPS
101 fMOD / 32 4 kSPS
110 fMOD / 16 8 kSPS
111 Do not use Do not use */
//--- CONFIG2: Configuration Register 2
//--- This register configures the test signal, clock, reference, and LOFF buffer
(0x01 << 7) + /*!< Bit 7 Must be set to '1' */
(0x00 << 6) + /*!< Bit 6 PDB_LOFF_COMP: Lead-off comparator power-down
This bit powers down the lead-off comparators.
0 = Lead-off comparators disabled (default)
1 = Lead-off comparators enabled */
(0x01 << 5) + /*!< Bit 5 PDB_REFBUF: Reference buffer power-down
This bit powers down the internal reference buffer so that the external reference can be used.
0 = Reference buffer is powered down (default)
1 = Reference buffer is enabled */
(0x00 << 4) + /*!< Bit 4 VREF_4V: Enables 4-V reference
This bit chooses between 2.42-V and 4.033-V reference.
0 = 2.42-V reference (default)
1 = 4.033-V reference */
(0x00 << 3) +
(0x00 << 3) + /*!< Bit 3 CLK_EN: CLK connection
This bit determines if the internal oscillator signal is connected to the CLK pin when an internal oscillator is used.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled */
(0x00 << 2) + /*!< Bit 2 Must be set to '0' */
(0x00 << 1) + /*!< Bit 1 INT_TEST: Test signal selection
This bit determines whether the test signal is turned on or off.
0 = Off (default)
1 = On; amplitude = �(VREFP � VREFN) / 2400 */
(0x00 << 0), /*!< Bit 0 TEST_FREQ: Test signal frequency
This bit determines the test signal frequency.
0 = At dc (default)
1 = Square wave at 1 Hz */
//--- LOFF: Lead-Off Control Register
//--- This register configures the lead-off detection operation
(0x00 << 5) + /*!< Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold
Comparator positive side Comparator negative side
000 = 95% (default) 000 = 5% (default)
001 = 92.5% 001 = 7.5%
010 = 90% 010 = 10%
011 = 87.5% 011 = 12.5%
100 = 85% 100 = 15%
101 = 80% 101 = 20%
110 = 75% 110 = 25%
111 = 70% 111 = 30% */
(0x00 << 4) + /*!< Bit 4 Must be set to '1' */
(0x00 << 2) + /*!< Bits[3:2] ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 6 nA (default)
01 = 22 nA
10 = 6 uA
11 = 22 uA */
(0x00 << 1) + /*!< Bit 1 Must be set to '0' */
(0x00 << 0), /*!< FLEAD_OFF: Lead-off frequency
This bit selects ac or dc lead-off.
0 = At dc lead-off detect (default)
1 = At ac lead-off detect at fDR / 4 (500 Hz for an 2-kHz output rate) */
//--- CH1SET: Channel 1 Settings
//--- This register configures the power mode, PGA gain, and multiplexer settings channels.
(0x00 << 7) + /*!< Bit 7 PD1: Channel 1 power-down
0 = Normal operation (default)
1 = Channel 1 power-down(1)
(1) When powering down channel 1, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001. */
(0x01 << 4) + /*!< Bits[6:4] GAIN1[2:0]: Channel 1 PGA gain setting
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12 */
(0x00 << 0), /*!< Bits[3:0] MUX1[3:0]: Channel 1 input selection
0000 = Normal electrode input (default)
0001 = Input shorted (for offset measurements)
0010 = RLD_MEASURE
0011 = MVDD(2) for supply measurement
0100 = Temperature sensor
0101 = Test signal
0110 = RLD_DRP (positive input is connected to RLDIN)
0111 = RLD_DRM (negative input is connected to RLDIN)
1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)
1001 = Route IN3P and IN3N to channel 1 inputs
1010 = Reserved
(2) For channel 1, (MVDDP � MVDDN) is [0.5(AVDD + AVSS)]; for channel 2, (MVDDP � MVDDN) is DVDD / 4. Note that to avoid
saturating the PGA while measuring power supplies, the gain must be set to '1'. */
//--- CH2SET: Channel 2 Settings
//--- This register configures the power mode, PGA gain, and multiplexer settings channels
(0x00 << 7) + /*!< Bit 7 PD2: Channel 2 power-down
0 = Normal operation (default)
1 = Channel 2 power-down(1)
(1) When powering down channel 2, make sure the input multiplexer is set to input short configuration. Bits[3:0] = 001. */
(0x01 << 4) + /*!< Bits[6:4] GAIN2[2:0]: Channel 2 PGA gain setting
000 = 6 (default)
001 = 1
010 = 2
011 = 3
100 = 4
101 = 8
110 = 12 */
(0x00 << 0), /*!< Bits[3:0] MUX2[3:0]: Channel 2 input selection
0000 = Normal electrode input (default)
0001 = Input shorted (for offset measurements)
0010 = RLD_MEASURE
0011 = MVDD(2) for supply measurement
0100 = Temperature sensor
0101 = Test signal
0110 = RLD_DRP (positive input is connected to RLDIN)
0111 = RLD_DRM (negative input is connected to RLDIN)
1000 = RLD_DRPM (both positive and negative inputs are connected to RLDIN)
1001 = Route IN3P and IN3N to channel 2 inputs
1010 = Reserved
(2) For channel 1, (MVDDP � MVDDN) is [0.5(AVDD + AVSS)]; for channel 2, (MVDDP � MVDDN) is DVDD / 4. Note that to avoid
saturating the PGA while measuring power supplies, the gain must be set to '1'. */
//--- RLD_SENS: Right Leg Drive Sense Selection
//--- This register controls the selection of the positive and negative signals from each channel for right leg drive derivation
(0x00 << 6) + /*!< Bits[7:6] CHOP[1:0]: Chop frequency
These bits determine PGA chop frequency
00 = fMOD / 16
01 = Reserved
10 = fMOD / 2
11 = fMOD / 4 */
(0x00 << 5) + /*!< Bit 5 PDB_RLD: RLD buffer power
This bit determines the RLD buffer power state.
0 = RLD buffer is powered down (default)
1 = RLD buffer is enabled */
(0x00 << 4) + /*!< Bit 4 RLD_LOFF_SENSE: RLD lead-off sense function
This bit enables the RLD lead-off sense function.
0 = RLD lead-off sense is disabled (default)
1 = RLD lead-off sense is enabled */
(0x00 << 3) + /*!< Bit 3 RLD2N: Channel 2 RLD negative inputs
This bit controls the selection of negative inputs from channel 2 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN2N */
(0x00 << 2) + /*!< RLD2P: Channel 2 RLD positive inputs
This bit controls the selection of positive inputs from channel 2 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN2P */
(0x00 << 1) + /*!< Bit 1 RLD1N: Channel 1 RLD negative inputs
This bit controls the selection of negative inputs from channel 1 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN1N */
(0x00 << 0), /*!< Bit 0 RLD1P: Channel 1 RLD positive inputs
This bit controls the selection of positive inputs from channel 1 for right leg drive derivation.
0 = Not connected (default)
1 = RLD connected to IN1P */
//--- LOFF_SENS: Lead-Off Sense Selection,
//--- This register selects the positive and negative side from each channel for lead-off detection,
//--- Note that the LOFF_STAT register bits should be ignored if the corresponding LOFF_SENS bits are set to '1'.
(0x00 << 6) + /*!< Bits[7:6] Must be set to '0' */
(0x00 << 5) + /*!< Bit 5 FLIP2: Current direction selection
This bit controls the direction of the current used for lead-off derivation for channel 2.
0 = Disabled (default)
1 = Enabled */
(0x01 << 4) + /*!< Bit 4 FLIP1: Current direction selection
This bit controls the direction of the current used for lead-off derivation for channel 1.
0 = Disabled (default)
1 = Enabled */
(0x01 << 3) + /*!< Bit 3 LOFF2N: Channel 2 lead-off detection negative inputs
This bit controls the selection of negative input from channel 2 for lead-off detection.
0 = Disabled (default)
1 = Enabled */
(0x01 << 2) + /*!< Bit 2 LOFF2P: Channel 2 lead-off detection positive inputs
This bit controls the selection of positive input from channel 2 for lead-off detection.
0 = Disabled (default)
1 = Enabled */
(0x01 << 1) + /*!< Bit 1 LOFF1N: Channel 1 lead-off detection negative inputs
This bit controls the selection of negative input from channel 1 for lead-off detection.
0 = Disabled (default)
1 = Enabled */
(0x01 << 0), /*!< Bit 0 LOFF1P: Channel 1 lead-off detection positive inputs
This bit controls the selection of positive input from channel 1 for lead-off detection.
0 = Disabled (default)
1 = Enabled */
//--- LOFF_STAT: Lead-Off Status
//--- This register stores the status of whether the positive or negative electrode on each channel is on or off.
//--- Ignore the LOFF_STAT values if the corresponding LOFF_SENS bits are not set to '1'.
(0x00 << 7) + /*!< Bit 7 Must be set to '0' */
(0x00 << 6) + /*!< Bit 6 CLK_DIV : Clock divider selection
This bit sets the modultar divider ratio between fCLK and fMOD. Two external clock values are supported: 512 kHz and 2.048 MHz.
0 = fMOD = fCLK / 4 (default, use when fCLK = 512 kHz)
1 = fMOD = fCLK / 16 (use when fCLK = 2.048 MHz) */
(0x00 << 5) + /*!< Bit 5 Must be set to '0' */
(0x01 << 4) + /*!< Bit 4 RLD_STAT: RLD lead-off status
This bit determines the status of RLD.
0 = RLD is connected (default)
1 = RLD is not connected */
(0x00 << 3) + /*!< Bit 3 IN2N_OFF: Channel 2 negative electrode status
This bit determines if the channel 2 negative electrode is connected or not.
0 = Connected (default)
1 = Not connected */
(0x00 << 2) + /*!< Bit 2 IN2P_OFF: Channel 2 positive electrode status
This bit determines if the channel 2 positive electrode is connected or not.
0 = Connected (default)
1 = Not connected */
(0x00 << 1) + /*!< Bit 1 IN1N_OFF: Channel 1 negative electrode status
This bit determines if the channel 1 negative electrode is connected or not.
0 = Connected (default)
1 = Not connected */
(0x00 << 0), /*!< Bit 0 IN1P_OFF: Channel 1 positive electrode status
This bit determines if the channel 1 positive electrode is connected or not.
0 = Connected (default)
1 = Not connected */
//--- RESP1: Respiration Control Register 1
//--- This register controls the respiration functionality. This register applies to the ADS1292R version only. For the
//--- ADS1291 and ADS1292 devices, 02h must be written to the RESP1 register.
(0x00 << 7) + /*!< Bit 7 RESP_DEMOD_EN1: Enables respiration demodulation circuitry
This bit enables and disables the demodulation circuitry on channel 1.
0 = RESP demodulation circuitry turned off (default)
1 = RESP demodulation circuitry turned on */
(0x00 << 6) + /*!< Bit 6 RESP_MOD_EN: Enables respiration modulation circuitry
This bit enables and disables the modulation circuitry on channel 1.
0 = RESP modulation circuitry turned off (default)
1 = RESP modulation circuitry turned on */
(0x00 << 2) + /*!< Bits[5:2] RESP_PH[3:0]: Respiration phase(1)
These bits control the phase of the respiration demodulation control signal.
RESP_PH[3:0] RESP_CLK = 32kHz RESP_CLK = 64 kHz
0000 0� (default) 0� (default)
0001 11.25� 22.5�
0010 22.5� 45�
0011 33.75� 67.5�
0100 45� 90�
0101 56.25� 112.5�
0110 67.5� 135�
0111 78.75� 157.5�
1000 90� Not available
1001 101.25� Not available
1010 112.5� Not available
1011 123.75� Not available
1100 135� Not available
1101 146.25� Not available
1110 157.5� Not available
1111 168.75� Not available
(1) The RESP_PH3 bit is ignored when RESP_CLK = 64 kHz. */
(0x01 << 1) + /*!< Bit 1 Must be set to '1' */
(0x00 << 0), /*!< Bit 0 RESP_CTRL: Respiration control
This bit sets the mode of the respiration circuitry.
0 = Internal respiration with internal clock
1 = Internal respiration with external clock */
//--- RESP2: Respiration Control Register 2
//--- This register controls the respiration and calibration functionality.
(0x00 << 7) + /*!< Bit 7 CALIB_ON: Calibration on
This bit is used to enable offset calibration.
0 = Off (default)
1 = On */
(0x00 << 3) + /*!< Bits[6:3] Must be '0' */
(0x00 << 2) + /*!< Bit 2 RESP_FREQ: Respiration control frequency (ADS1292R only)
This bit controls the respiration control frequency when RESP_CTRL = 0. This bit must be written with '1' for the ADS1291
and ADS1292.
0 = 32 kHz (default)
1 = 64 kHz */
(0x01 << 1) + /*!< Bit 1 RLDREF_INT: RLDREF signal
This bit determines the RLDREF signal source.
0 = RLDREF signal fed externally
1 = RLDREF signal (AVDD � AVSS) / 2 generated internally (default) */
(0x01 << 0), /*!< Bit 0 Must be set to '1' */
//--- GPIO: General-Purpose I/O Register
//--- This register controls the GPIO pins.
(0x00 << 4) + /*!< Bits[7:4] Must be '0' */
(0x03 << 2) + /*!< Bits[3:2] GPIOC[2:1]: GPIO 1 and 2 control
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)*/
(0x00 << 0), /*!< Bits[1:0] GPIOD[2:1]: GPIO 1 and 2 data
These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the
GPIOD has no effect. GPIO is not available in certain respiration modes. */
