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DAC38J82: Serdes PLL cannot be locked, and FIFO reports an error

Part Number: DAC38J82
Other Parts Discussed in Thread: LMK04828

Hi team,

When one of our customers used DAC38J82 for development, Serdes PLL could not be locked after configuring parameters, and FIFO reported an error;

The customers use DAC3XJ8X GUI v1.3 software generates the required parameters. No changes have been made after generating the parameters. The parameter configuration is shown in the figure below.

LMK04828
0x00 0x00
0x02 0x00
0x100 0x01
0x101 0x55
0x103 0x00
0x104 0x20
0x105 0x00
0x106 0xF0
0x107 0x11
0x108 0x61
0x109 0x55
0x10B 0x01
0x10C 0x20
0x10D 0x00
0x10E 0xF0
0x10F 0x76
0x110 0x08
0x111 0x55
0x113 0x00
0x114 0x00
0x115 0x00
0x116 0xF9
0x117 0x00
0x118 0x18
0x119 0x55
0x11B 0x00
0x11C 0x20
0x11D 0x00
0x11E 0xF9
0x11F 0x00
0x120 0x10
0x121 0x55
0x123 0x00
0x124 0x00
0x125 0x00
0x126 0xF9
0x127 0x11
0x128 0x08
0x129 0x55
0x12B 0x00
0x12C 0x00
0x12D 0x00
0x12E 0xF9
0x12F 0x00
0x130 0x08
0x131 0x55
0x133 0x00
0x134 0x20
0x135 0x00
0x136 0xF9
0x137 0x01
0x138 0x40
0x139 0x02
0x13A 0x00
0x13B 0xA0
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x00
0x140 0x00
0x141 0x00
0x142 0x00
0x143 0x12
0x144 0xFF
0x145 0x00
0x146 0x10
0x147 0x12
0x148 0x02
0x149 0x42
0x14A 0x02
0x14B 0x16
0x14C 0x00
0x14D 0x00
0x14E 0xC0
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
0x153 0x00
0x154 0x78
0x155 0x00
0x156 0x78
0x157 0x00
0x158 0x96
0x159 0x00
0x15A 0x78
0x15B 0xF4
0x15C 0x20
0x15D 0x00
0x15E 0x00
0x15F 0x0B
0x160 0x00
0x161 0x01
0x162 0x44
0x163 0x00
0x164 0x00
0x165 0x0C
0x166 0x00
0x167 0x00
0x168 0x0C
0x169 0x5B
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
0x17C 0x15
0x17D 0x0F
DAC_RESET
0x00 0x1
DAC3XJ8X
0x00 0x0018
0x01 0x0003
0x02 0x2002
0x03 0xA300
0x04 0xF0F0
0x05 0xFF07
0x06 0xFFFF
0x07 0x3100
0x08 0x0000
0x09 0x0000
0x0A 0x0000
0x0B 0x0000
0x0C 0x0400
0x0D 0x0400
0x0E 0x0400
0x0F 0x0400
0x10 0x0000
0x11 0x0000
0x12 0x0000
0x13 0x0000
0x14 0x0000
0x15 0x0000
0x16 0x0000
0x17 0x0000
0x18 0x0000
0x19 0x0000
0x1A 0x0023
0x1B 0x0000
0x1E 0x9999
0x1F 0x9980
0x20 0x8008
0x22 0x1B1B
0x23 0x01FF
0x24 0x0020
0x25 0x2000
0x26 0x0000
0x2D 0x0001
0x2E 0xFFFF
0x2F 0x0004
0x30 0x0000
0x31 0x1000
0x32 0x0000
0x33 0x0000
0x34 0x0000
0x3B 0x0000
0x3C 0x0050
0x3D 0x0088
0x3E 0x0148
0x3F 0x0000
0x46 0x1882
0x47 0x01C8
0x48 0x3143
0x49 0x0000
0x4A 0x0F3E
0x4B 0x1200
0x4C 0x1303
0x4D 0x0100
0x4E 0x0F4F
0x4F 0x1C61
0x50 0x0000
0x51 0x00DC
0x52 0x00FF
0x53 0x0000
0x54 0x00FC
0x55 0x00FF
0x56 0x0000
0x57 0x00FF
0x58 0x00FF
0x59 0x0000
0x5A 0x00FF
0x5B 0x00FF
0x5C 0x1133
0x5E 0x0000
0x5F 0x3210
0x60 0x5764
0x61 0x0211
0x64 0x0001
0x65 0x0001
0x66 0x0001
0x67 0x0001
0x68 0x7709
0x69 0x0000
0x6A 0x0000
0x6B 0xBD07
0x6C 0x0007
0x6D 0x0090
0x6E 0x0000
0x6F 0x0000
0x70 0x0000
0x71 0x0000
0x72 0x0000
0x73 0x0000
0x74 0x0000
0x75 0x0000
0x76 0x0000
0x77 0x0000
0x78 0x0000
0x79 0x0000
0x7A 0x0000
0x7B 0x0000
0x7C 0x0000
0x7D 0x0000

Best Regards,

Amy Luo

  • Amy,

    This error is usually related to a clocking issue. Is this a custom board or the TI EVM?

    1. Is the FPGA and DAC receiving a proper clock and SYSREF (frequency & amplitude)?

    2. What is the status of SYNC? Is the DAC sending this high after CGS?

    3. Are the link parameters correct on both the DAC and FPGA (K, L, M, F, S, ect...)?

    4. Is the DAC issued a hard reset after clocks and power are provided?

    Please run the NCO only test attached which will verify the DAC38J82 SPI, clocks and power are correct.

    Regards,

    Jim

    7840.DAC38J84 100MHz NCO Test.pptx

  • Hi Jim,

    Thank you very much for your reply. In response to your questions and test results, we make the following reply:

    Q: This error is usually related to a clocking issue. Is this a custom board or the TI EVM?

    A: The debugging board is custom board and is a combination of LMK04828+DAC38J82.

    Q: 1. Is the FPGA and DAC receiving a proper clock and SYSREF (frequency & amplitude)?

    A: since no test points are reserved, the clock status can only be inferred from the side. Check via ILA from inside the FPGA that the clock and SYSREF frequency received by the FPGA are correct. Since only the parameters of the clock output from LMK04828 to DAC and the clock output to FPGA are different, and when DAC38J82 adopts PLL configuration mode, the PLL of DAC can be locked. I think the clock received by DAC is correct.

    Q: 2. What is the status of SYNC? Is the DAC sending this high after CGS?

    A: After the DAC parameter configuration is completed, SYNC remains high all the time, but it is uncertain when it will be raised.

    Q: 3. Are the link parameters correct on both the DAC and FPGA (K, L, M, F, S, ect...)?

    A: After many checks, the parameter configurations of the two are consistent.

    Q: 4. Is the DAC issued a hard reset after clocks and power are provided?

    A: The actual work flow is: first configure the parameters of LMK04828. After the device is configured, the FPGA outputs low pulse, resets the DAC, and then configure the DAC parameters.

    Q: Please run the NCO only test attached which will verify the DAC38J82 SPI, clocks and power are correct.

    A: According to the information you provided, combined with the device model, the screenshot of parameter configuration is as follows:

    DAC38J82 and LMK04828 parameter files and configuration sequence files are also attached

    3882_4lanes.cfg

    LMK04828_HexRegisterValues.txt
    R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x010000
    R257	0x010155
    R258	0x010255
    R259	0x010301
    R260	0x010422
    R261	0x010500
    R262	0x0106F0
    R263	0x010711
    R264	0x010864
    R265	0x010955
    R266	0x010A55
    R267	0x010B04
    R268	0x010C22
    R269	0x010D00
    R270	0x010EF0
    R271	0x010F77
    R272	0x011008
    R273	0x011155
    R274	0x011255
    R275	0x011300
    R276	0x011402
    R277	0x011500
    R278	0x0116F9
    R279	0x011700
    R280	0x01180C
    R281	0x011955
    R282	0x011A55
    R283	0x011B00
    R284	0x011C22
    R285	0x011D00
    R286	0x011EF0
    R287	0x011F33
    R288	0x01200C
    R289	0x012155
    R290	0x012255
    R291	0x012300
    R292	0x012422
    R293	0x012500
    R294	0x0126F0
    R295	0x012711
    R296	0x012808
    R297	0x012955
    R298	0x012A55
    R299	0x012B00
    R300	0x012C02
    R301	0x012D00
    R302	0x012EF9
    R303	0x012F00
    R304	0x01300C
    R305	0x013155
    R306	0x013255
    R307	0x013300
    R308	0x013422
    R309	0x013500
    R310	0x0136F1
    R311	0x013731
    R312	0x013825
    R313	0x013902
    R314	0x013A03
    R315	0x013BC0
    R316	0x013C00
    R317	0x013D08
    R318	0x013E01
    R319	0x013F00
    R320	0x01408A
    R321	0x014100
    R322	0x014200
    R323	0x014312
    R324	0x014400
    R325	0x01457F
    R326	0x014600
    R327	0x01471A
    R328	0x014802
    R329	0x014942
    R330	0x014A02
    R331	0x014B16
    R332	0x014C00
    R333	0x014D00
    R334	0x014EC0
    R335	0x014F7F
    R336	0x015003
    R337	0x015102
    R338	0x015200
    R339	0x015300
    R340	0x015478
    R341	0x015500
    R342	0x015678
    R343	0x015700
    R344	0x015896
    R345	0x015900
    R346	0x015A78
    R347	0x015BD4
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F0B
    R352	0x016000
    R353	0x016101
    R354	0x016244
    R355	0x016300
    R356	0x016400
    R357	0x01650C
    R369	0x0171AA
    R370	0x017202
    R380	0x017C15
    R381	0x017D33
    R358	0x016600
    R359	0x016700
    R360	0x01680C
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E13
    R371	0x017300
    R386	0x018200
    R387	0x018300
    R388	0x018400
    R389	0x018500
    R392	0x018800
    R393	0x018900
    R394	0x018A00
    R395	0x018B00
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    

    spi_3882.txt
            send_data[0  ] <= 24'h4A_0F_3E;
            send_data[1  ] <= 24'h24_00_00;
            send_data[2  ] <= 24'h5C_00_00;
            send_data[3  ] <= 24'h00_01_18;                              
            send_data[4  ] <= 24'h01_00_03;                              
            send_data[5  ] <= 24'h02_20_50;                              
            send_data[6  ] <= 24'h03_A3_00;                              
            send_data[7  ] <= 24'h04_F0_F0;                              
            send_data[8  ] <= 24'h05_FF_07;                              
            send_data[9  ] <= 24'h06_FF_FF;                              
            send_data[10 ] <= 24'h07_31_00;                              
            send_data[11 ] <= 24'h08_00_00;                              
            send_data[12 ] <= 24'h09_00_00;                              
            send_data[13 ] <= 24'h0A_00_00;                              
            send_data[14 ] <= 24'h0B_00_00;                              
            send_data[15 ] <= 24'h0C_04_00;                              
            send_data[16 ] <= 24'h0D_04_00;                              
            send_data[17 ] <= 24'h0E_04_00;                              
            send_data[18 ] <= 24'h0F_04_00;                              
            send_data[19 ] <= 24'h10_00_00;                              
            send_data[20 ] <= 24'h11_00_00;                              
            send_data[21 ] <= 24'h12_00_00;                              
            send_data[22 ] <= 24'h13_00_00;                              
            send_data[23 ] <= 24'h14_38_E4;                              
            send_data[24 ] <= 24'h15_E3_8E;                              
            send_data[25 ] <= 24'h16_22_B8;                              
            send_data[26 ] <= 24'h17_00_00;                              
            send_data[27 ] <= 24'h18_00_00;                              
            send_data[28 ] <= 24'h19_00_00;                              
            send_data[29 ] <= 24'h1A_00_20;                              
            send_data[30 ] <= 24'h1B_00_00;
            send_data[31 ] <= 24'h1E_99_99;                              
            send_data[32 ] <= 24'h1F_99_80;                              
            send_data[33 ] <= 24'h20_80_08;                              
            send_data[34 ] <= 24'h22_1B_1B;                              
            send_data[35 ] <= 24'h23_01_FF;                              
            send_data[36 ] <= 24'h25_40_00;
            send_data[37 ] <= 24'h26_00_00;
            send_data[38 ] <= 24'h2D_00_01;
            send_data[39 ] <= 24'h2E_FF_FF;
            send_data[40 ] <= 24'h2F_00_05;
            send_data[41 ] <= 24'h30_00_00;
            send_data[42 ] <= 24'h31_10_00;
            send_data[43 ] <= 24'h32_00_00;
            send_data[44 ] <= 24'h33_00_00;
            send_data[45 ] <= 24'h34_00_00;
            send_data[46 ] <= 24'h3B_08_00;
            send_data[47 ] <= 24'h3C_02_28;
            send_data[48 ] <= 24'h3D_00_88;
            send_data[49 ] <= 24'h3E_01_28;
            send_data[50 ] <= 24'h3F_00_00;
            send_data[51 ] <= 24'h46_18_82;
            send_data[52 ] <= 24'h47_01_C8;
            send_data[53 ] <= 24'h48_31_43;
            send_data[54 ] <= 24'h49_00_00;
            send_data[55 ] <= 24'h4B_12_00;
            send_data[56 ] <= 24'h4C_13_03;
            send_data[57 ] <= 24'h4D_01_00;
            send_data[58 ] <= 24'h4E_0F_4F;
            send_data[59 ] <= 24'h4F_1C_61;
            send_data[60 ] <= 24'h50_00_00;
            send_data[61 ] <= 24'h51_00_DC;
            send_data[62 ] <= 24'h52_00_FF;
            send_data[63 ] <= 24'h53_00_00;
            send_data[64 ] <= 24'h54_00_FC;
            send_data[65 ] <= 24'h55_00_FF;
            send_data[66 ] <= 24'h56_00_00;
            send_data[67 ] <= 24'h57_00_FF;
            send_data[68 ] <= 24'h58_00_FF;
            send_data[69 ] <= 24'h59_00_00;
            send_data[70 ] <= 24'h5A_00_FF;
            send_data[71 ] <= 24'h5B_00_FF;
            send_data[72 ] <= 24'h5E_00_00;
            send_data[73 ] <= 24'h5F_32_10;
            send_data[74 ] <= 24'h60_57_64;
            send_data[75 ] <= 24'h61_02_11;
            send_data[76 ] <= 24'h6D_00_90;
            send_data[77 ] <= 24'h6E_00_00;
            send_data[78 ] <= 24'h6F_00_00;
            send_data[79 ] <= 24'h70_00_00;
            send_data[80 ] <= 24'h71_00_00;
            send_data[81 ] <= 24'h72_00_00;
            send_data[82 ] <= 24'h73_00_00;
            send_data[83 ] <= 24'h74_00_00;
            send_data[84 ] <= 24'h75_00_00;
            send_data[85 ] <= 24'h76_00_00;
            send_data[86 ] <= 24'h77_00_00;
            send_data[87 ] <= 24'h78_00_00;
            send_data[88 ] <= 24'h79_00_00;
            send_data[89 ] <= 24'h7A_00_00;
            send_data[90 ] <= 24'h7B_00_00;
            send_data[91 ] <= 24'h7C_00_00;
            send_data[92 ] <= 24'h7D_00_00;
            send_data[93 ] <= 24'h24_00_20;
            send_data[94 ] <= 24'h5C_11_33;
            send_data[95 ] <= 24'h4A_0F_3E;
            send_data[96 ] <= 24'h4A_0F_3F;
            send_data[97 ] <= 24'h4A_0F_21;
            send_data[98 ] <= 24'h03_A3_01;
            send_data[99 ] <= 24'h64_00_00;
            send_data[100] <= 24'h65_00_00;
            send_data[101] <= 24'h66_00_00;
            send_data[102] <= 24'h67_00_00;
            send_data[103] <= 24'h68_00_00;
            send_data[104] <= 24'h69_00_00;
            send_data[105] <= 24'h6A_00_00;
            send_data[106] <= 24'h6B_00_00;
            send_data[107] <= 24'h6C_00_00;
            send_data[108] <= 24'h00_00_00;

    The final output signal spectrum is as follows:

    Best Regards,

    Amy

  • Amy,

    SIF_SYNC must be toggled for the NCO values to get updated. After all of the DAC registers are loaded, they need to do the following writes:

    Address   Data

    0x1F        0x9980

    0x1F        0x9982

    0x1F        0x9980

    They should get a 100MHz output after doing this.

    Regards,

    Jim 

  • Hi Jim,

    Thank you very much for your guidance. After modification, 100MHz output is indeed obtained. According to this, can we get the reason why Serdes PLL cannot be locked and FIFO error is reported?

    Best Regards,

    Amy

  • Amy,

    After the DAC and FPGA is configured, have the customer reset the DAC JESD core and issue LMK SYSREF pulses using the register writes shown below.  I have also attached a start up sequence guide for them to try.

    Regards,

    Jim 

     7635.DAC38J84 SYSREF Configuration.docx

  • Hi Jim,

    According to your suggestion, after resetting the DAC JESD core, add the register that triggers the LMK SYSREF pulse, and read back the status of 0x6c is still 0x0f, but the error of FIFO is no longer reported, but I suspect that the change of FIFO is due to the closing of the serial channel. In addition, I have two questions:

    1. Is SYSREF related to SerdesPLL  locking?

    2. Can the clock in the SerdesPLL loop be output through the ALARM pin? Can it be connected to the FPGA through I/O for viewing?

    Regards,

    Amy

  • Amy,

    1. No. Either the DAC input clock or the DAC PLL VCO is used by the Serdes PLL. The FIFO errors and others will not be valid until the Serdes PLL is locked and they are cleared by writing "0" to them.

    2. No. No.

    3. Makes sure the customer writes a "0" to clear the alarms before reading them in register 0x6C. Make sure bit 15 is set to "0" in register 0x3B if not using the DAC PLL.

    4. What is the Serdes reference clock divider set to? This is bits 14:11 in register 0x3B.

    5. If the Serdes PLL is not locked, CGS did not pass and the link should be stuck with SYNC low and the FPGA constantly sending  0xBCBC (K28.5 characters). Is this true?