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ADC09QJ1300-Q1: how to map the different lane's data to rx_tdata[255:0]

Shubiao Wang
Intellectual 1490 points
Part Number: ADC09QJ1300-Q1

and have a problem on debuging  jesd204  interface. 

     

Hi There,

Customer is working on jesd204  interface debugging.   

 Test condition: adc09qj1300-q1 which is the data transmit end.  And also data receive end is FPGA,  xilinx's  ZYNQ series chip that is 7z100 chip. Data tx send adc samples to rx via jesd204b.  ADC's  configuration parameter:  JMODE = 0(F = 8),   K = 4,  lane num =8,   Fs = 1GSPS.   7z100 's  K and F is the same with adc chip,  and  Serdes  speed  is 6.25Gbps.   Now,  at 7z100,  i  saw jesd204b links up  and can get adc tx parameter via AXI4-lite interface.

question: In  FPGA, customer wants to de-map the received data whose format is:  rx_tvalid、rx_tdata[255:0]、rx_start_of_frame[3:0],  rx_end_of_frame[3:0]、rx_start_of_multiframe[3:0]、rx_start_of_multiframe[3:0].  7z100's  user clock is  rx_core_clk， and one clock corresponding to 256 bits(rx_tdata[255:0]). 

how can we map the different lane's data to rx_tdata[255:0]!  even with the explanation on page 79,  Table 8-21 of theADC09QJ1300-Q1 datasheet, we still don't know how to do the mapping.

BRs,

Shubiao

  • 0
    TI__Mastermind 20541 points

    Hi, 

    Can you please have the customer change the output data mode on the ADC to Transport layer test pattern and then generate the ILA data from all 8 LANES and share the data with us and then it will be easy to explain the mapping. 

    To enable the transport layer test pattern do the following register writes. 

    Address VALUES

    0x200     0x00

    0x205     0x05

    0x205     0x01

    Regards,

    Neeraj 

  • 0 in reply to Neeraj Gill
    Prodigy 40 points

    Hi， thank you for your patient explanation. I have tried your advise. The ADC(adc09qj1300-q1) configuration is :

    Address VALUES
    0x000 0xb0 reset the entire chip and spi interface
    0x200 0x00 JESD_EN = 0
    0x201 0x00 JMODE = 0
    0x205 0x05 Transport Layer test mode
    0x200 0x01 JESD_EN = 1

    But, fpga side(AXI stream) does not receive any data as follow :

    SO, how can i use test mode ? Does fpga need some configuration ?

  • 0 in reply to zeng xiangdong
    TI__Mastermind 20541 points

    Hi,

    Yes the FPGA will need to be configured as you would do in normal mode. The only difference here is the data coming from the ADC is a fixed pattern depending on the jesd lanes. Please configure the FPGA and go though all cgs ILA etc process and capture the data and share it with us. 

    Regards,

    Neeraj  

  • 0 in reply to Neeraj Gill
    Prodigy 40 points

    Hi, 

    I have tried a lot  to  configure ADC, but failed.  When ADC  in normal operation(JEST = 0),  Xilinx ZYNQ can receive the data, and  rx_tvalid =1, rx_tdata[255:0] have valid adc sample data. But  in  "Transport Layer test mode",  JTEST = 5, Xilinx ZYNQ also can not receive any data, rx_tvalid =0.

    Below is the ADC's configuration:

    0x000 0xb0 reset the entire chip and spi interface
    0x200 0x00 JESD_EN = 0

    0x061 0x00 CAL_en = 0 
    0x201 0x00 JMODE = 0

    0x202 0x03 K =4

    0x204 0x02 not scramble
    0x205 0x05 Transport Layer test mode

    0x057 0x01  TRIGOUT_MODE = 1

    0x057 0x81  TRIGOUT_EN = 1

    0x061 0x01 CAL_en = 1 
    0x200 0x01 JESD_EN = 1

    Actually,  in normal  operation, we need not config XIlinx ZYNQ throught  it's  AXI4-Lite interface,  because when  using  Xilinx's JESD204B  ip core, we have selected  basic work parameter.  So theoretically,  I should config the adc only.   Could you please check my configuration,  and give me some advise to run it in test pattern.  Thks ! 

  • 0 in reply to zeng xiangdong
    TI__Mastermind 20541 points

    Hi,

    Can you please try the ramp test pattern and see if you are seeing ramp on each lane?

    Regards,

    Neerraj

  • 0 in reply to Neeraj Gill
    Prodigy 40 points

    It still  does not work.  ZYNQ can‘t receive data.   The ADC  configuration step is wrong  ？  Could you please  give me  an example config step .  Thks ! 

  • 0 in reply to zeng xiangdong
    TI__Mastermind 20541 points

    HI Zeng,

    If the FPGA works with normal data and not in test mode to me it looks like a timing issue. Can you add some delay once you enable JESD after setting the test mode and issue if your issue goes away. 

    Regards,

    Neeraj