ADS8353-Q1: ADS8353-Q1 SPI mode and timing

Lukas Valda

Part Number: ADS8353-Q1

Hello,

I have some troubles with the SPI interface of the ADS8353-Q1.

I have found out that I can correctly read and write the user programmable registers using SPI mode 1. In this case, the read data is shifted 1 bit left. The same applies to the conversion result. The conversion result can be correctly read when the SPI mode 0 is used instead. However, the user programmable registers cannot be read and written anymore.

This device should latch the SDI data as well as update SDO data on the falling edge of the SCLK according to the datasheet. The standard SPI interface latches the SDI data on one edge and updates the SDO data on another edge. In other word this device does not have the (standard) SPI interface. Is this right?

over 3 years ago

0 Ryan Andrews over 3 years ago

TI__Guru 66186 points

Hello Lukas,

Thank you for your post.

You are correct that the SCLK falling is responsible both for latching each bit and for shifting out the next bit on SDO. This is needed to support the maximum throughput of the ADS8353-Q1. Tables 9 and 10 list the data launch edges for single and dual SDO modes.

For reading and writing registers, the first 16 falling edges of each frame are used to latch the device command word. You may not be sending enough SCLK falling edges to execute the command.

Let us know if you still need help with this issue.

Regards,

Ryan