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ADC12DJ5200RF: How to determine the device clock frequency going to the FPGA

Peter Cheng
Prodigy 70 points
Part Number: ADC12DJ5200RF

Assuming that my sampling frequency is 5GHz, is the device clock going to the FPGA also required to be 5GHz?  Or can it be a much lower frequency?  If so, how do I determine calculate the frequency?

  • +1
    TI__Guru* 91947 points

    Peter,

    Here are the steps to calculate the frequency:

    1. Compute the line rate (LR) of the JESD link = Fclk * R (the R ratio is available in the JMODE table of the datasheet)
    2. Once the LR is computed, the reference clock frequency depends on the width of the JESD IP and the encoding
      1. For 8b10b encoding
    1. If IP is 32 bits wide : reference clock = LR/40
    2. If IP is 64 bits wide : reference clock = LR/80
      1. For 64b66b encoding
    1. If IP is 32 bits wide : reference clock = LR/33
    2. If IP is 64 bits wide : reference clock = LR/66

    Regards,

    Jim