ADS1602: Datasheet question asking

Hello Jason,

In order to synchronize multiple ADC's, the SYNC pulse from the host MCU should operate from the same clock as the ADC.  This is necessary to meet the Timing Requirements in Figure 1 of the datasheet.

1.  Yes, it is recommended that the host controller (MCU, FPGA, and so forth) operate from a common clock oscillator as the ADS1602.  This will make it easier to meet the SYNC timing requirements relative to the CLK edge.

2.  You can synchronize the SYNC pulse to the ADS1602 CLK by using a D flipflop, where the clock input of the D-type flip-flop is /CLK, and the output is the synchronized version of SYNC pulse.  

3.  The clock must be present and stable before the synchronization pulse.  Yes, After the SYNC pulse, the ADC will generate FSO, SCLK, and DOUT.  Follow the timing diagrams in Figure 1 and Figure 2 for details on these signals.

4.  AINP and AINN can range from -0.1V to 4.6V with respect to AGND.  The difference (AINP-AINN) must range from -VREF to +VREF.  If VREF=3V typical, then the range of (AINP-AINN) will be limited from -3V to +3V differential.  Please take a look at this TI Precision Labs presentation that discusses differential inputs in more detail.

Regards,
Keith Nicholas
Precision ADC Applications

Hi Jason,

As long as the MCU operates from the same CLK source as the ADC, the output will either transition on the rising or falling edge of CLK (plus some propagation delay).  You can ensure that the SYNC signal changes on the falling edge of CLK by using a synchronization circuit composed of an inverter and D-type flip-flop.

Regards,
Keith

Hello Jason,

If the timing of your SYNC signal will always meet the setup and hold time requirements for the D-type flip-flop (for example, if implementing inside an FPGA), then you only need a single flip-flop.  The additional flip-flop allows the SYNC signal to be unsynchronized to the CLK signal; adding 2 flip-flops creates a digital synchronizer.

Here is a link that describes this circuit in more detail.

https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf

Regards,
Keith

Hi Jason,

I am not sure why the link does not work for you.  There are many links that you can search for using the below keywords:

Two flip flop synchronizer

Digital synchronization

Pulse synchronization

Synchronizing circuits

https://inst.eecs.berkeley.edu/~cs150/sp12/agenda/lec/lec16-synch.pdf

https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf

https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/

Regards,
Keith

Hello Jason,

1. There are two digital inputs that must be provided to the ADS1602, SYNC and CLK.  CLK should be continuous and is fixed at a typical frequency of 40MHz.  The SYNC pulse should be at least 1 CLK period in width (typically longer) and aligned with the falling edge of CLK as discussed previously.  After the SYNC pulse occurs, the FSO will go low and stay low for 833 CLK periods.  This allows time for the internal digital filter to reset.  After this delay, the FSO pin will pulses high with a width of 1 CLK period every data output period, or 16 CLK periods.  SCLK is an output clock operating at the same frequency as CLK, but delayed by up to 15nsec and aligned to the DOUT pin and launces data on the rising edge of SCLK.

2.  If you set the input common mode voltage to the typical level of 1.45V, then yes, the input voltage on each input for full scale differential of +3V will be -0.05V to +2.95V.  However, you can set the common mode level to 1.5V, which will allow for an input range of 0V to +3V.  The inputs can be operated in the range of -0.1V < (AINN or AINP) < +4.2V.  This allows the common mode range to be from 1.4V to 2.7V for optimum performance.

Regards,
Keith