ADS54J60EVM: Connect to Xilinx VCU118 board

Richard,

I do not see any reason why this should not work. We haver tested the VCU118 with another TI ADC using the TI JESD IP with no issues. The ADS54J60EVM does have FMC pin H2 open which is labeled as "FMCP_HSPC_H_PRSNT_M2C_B" on the VCU118 schematic. Not sure if this needed to be tied to GND on the ADC board or not. The EEPROM on the ADC board that connects to the FMC is not programmed, which may be an issue if the firmware is expecting info from this part.

What is the status of SYNC? Does the FPGA ever send this high?

Regards,

Jim  

The Xilinx JESD204 core is setup in an identical way to the one used on the KCU105. The sync signal is one of the ones I have "chipscope" on , I can't tell if it it is driven when the core first powers up but if I force a core reset I can see it go low and as mentioned the rx_reset_done line finally goes high too. The KCU105 build doesn't require any extra resetting.

Both designs are using refClk as coreClk. It would be possible to use glblClock on the KCU105 board as CL_LA0_P/M signal from the LMK gets mapped to a global clock pin on the FGPA. On the VCU118 it is not connected to a clock bin so I switched to using refClk as coreClk for both designs.

There is no FW trying to read an E2 in either design so that shouldn't be an issue. Equally neither build use that board present signal.

I power the TI board with an external supply is there any chance this clashes with the VCU118 somehow, although I think if that wasn't working I wouldn't get my clocks from the LMK or the idle sequences from the ADC.

Out of interest does the other TI ADC boards that work have the same mapping of ADC signals and clocks onto the FMC connector than the ADS54J60EVM. If so then could you provide the reference design that worked for the other boards as it should work for this one. 

Thanks for the reference design although that really is quite a different device so i'm not sure that confirms the ADS54J60EVM can work with the VCU118.

But given it seems to be most of the way there, and I can see it drop the sync signal when I reset and get the bcbcbcbc idle characters, just no data. I would question the reset circuit but as I said the exact same design works fine on the KCU105. 

Is SYNC ever going back high? If not, see if you can toggle this manually and see is the ADC starts sending the ILA data. What configuration files are you using for the ADC EVM? Make sure to press the hard reset on the ADC EVM after the LMK config file has been loaded and before loading the ADC config file.  

Yes, I can capture the SYNC going high. I'm using the exact same config files I used to make things work on the KCU105, although as I've mentioned before I didn't even need to prod a reset in that case the whole thing just worked and data was flowing.

Is Chipscope showing any ILA data?

What should I see for the ILA, if I turn turn on the JESD test pattern with the GUI I still just see the bcbcbcbc. 

In the period before the sync is done there are zeros on the gt<x>_rxdata lines and the gt3_rxnotintable bits are high for each lane.

The setup scripts turn off the syref from the LMK to the ADCs, I tried re-enabling it before I reset the JESD core (which as I've mentioned wasn't even necessary on the KCU105) and this caused everything to go crazy with the sync line continually toggling and the bcbc characters now actually coming out of the cores main rxData port.  

AS further notes, the constant D21.5 option puts out b5b5b5b5. K28.5 puts out the bcbcbcbc. The 12 octet RPAT creates some random data on those buses between the phy and the main core but doesn't cause anything to come out of the main output.

Richard, 

There are some bugs with the GUI. I would stick to just using config files. I would expect the ADC to start sending ILA data as shown in attached file right after SYNC goes high. I am checking with our firmware team to see if they can generate a project using the VCU118 with the ADS54J60EVM.

Regards,

Jim

I'm definitely not seeing any data like that. As an experiment I actually just used the button to hold the ADC in reset and that doesn't change what i'm seeing, I still get the idle sequence even during reset so I guess that's actually the phy producing that rather than the ADC.

The reset button will freeze the ADC. I would expect no output. Have you tried using the TI JESD204B/C IP instead of the Xilinx IP? This IP is available for free and was used on the reference design I sent you. 

Regards,

Jim

My point with the reset is that using the indicators I have available the status flags and data bus look the same whether I'm holding the core in reset or not.

I did submit a request for a TI JESD204B core but haven't received anything although having seen that the example design you sent for just full of xci files I assume that you where just configuring up a Xilnix core yourself. We tend to use VHDL instead of system verilog but from what I could see there wasn't anything in there that was a separate IP from the xilinx cores. 

Richard,

The example I sent did not include the TI IP core. This core uses nothing related to Xilinx. You will get this IP once you receive the package you requested. How long ago was this request made? I can look into getting it expedited.

Regards,

Jim  

So the bit about being used in the design you sent me isn't correct then?

I submitted the request at the same time has I made the original post here 5 days ago. Although I have to admit i'm not sure the process asked for enough details to correctly make a core.