This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8344: Any way to detect ADS8344 power cycle?

Genius 15770 points
Part Number: ADS8344
Other Parts Discussed in Thread: ADS8354

Hello,

 

My customer has a question for ADS8344.

 

The datasheet says that clock mode should be set before setting to power-down mode(PD1=PD0=0) when power is first applied.

In the customer’s system, ADS8344 and MCU are isolated. Then only ADS8344 power could be down temporarily by noise although MCU power is active.

Then MCU may not be aware ADS8344 power is temporarily down and they can’t find any good way to detect it.

Is there any way to detect ADS8344 power cycle?

 

Regards,

Oba

  • Can you monitor the state of BUSY in your system Oba?  Compare Figure 5 and Figure 6 in the ADS8344 datasheet.  BUSY behaves differently with EXT versus INT clock mode.

  • Hello Tom,

    Thanks for your reply.

    There is no description about the default status of the clock mode right after the power-up, but from the below post, the default setting seems to be disabled and busy behavior looks different from fig 5 and 6.

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/238904/ads8344-first-conversion?

     

    When the host continues to send the command with PD0=PD1=0 even after ADS8354 had a power cycle, what happens? And how to detect it?

     

    Regards,

    Satoshi Obata

     

     

     

     

  • So, which clock mode do you intend to use?  From the other post, you can see the behavior of BUSY after power up.  From figures 5 and 6, you see the expected behavior of BUSY during normal operation.  For external clock mode operation, you would expect BUSY to be high following the 8th clock cycle.  For internal clock mode, BUSY should go low after the 8th clock.  If you are not monitoring BUSY at all and simply intend to use a state based machine (an FPGA for example) then no, there is no way to detect an inadvertent power cycle.  If you are monitoring BUSY, then you could conceivably put a case statement in your code to look at the state of BUSY after the 8th SCLK and decide whether or not you need to do an extra 'dummy' conversion cycle.