DDC118: Only 4 channels visible

Hi Nicola,

Please share the timing diagram for the CONV (integration time) and DVALID signals along with the DOUT and DCLK.

Hi Praveen, thanks for your interest!
Here you can see 2 screen shots:

Ch1: DCLK
Ch2: DOUT
Ch3: DVALID
Ch4: CONV

The second image is just a zoom in in time.
These signals were acquired with TEST=HIGH and no pulse, so it is very easy to see the 4 channels, due to the leading zeros.

Note that there is a delay between CONV and DCLK, I introduced it as part of the debug, with only 1 clk of delay there was no difference.
Similarly, DCLK stays on for a while after DOUT finished transmitting, but I'll reduce it when everything is working.

PS: The marking on the chip is DDC118, TI OBZ, F6L4. My first doubt was that it was a mislabled DDC114, but it looks like the working channels are 5,6,7 and 8, so the pinout doesn't corresponds.

Thanks for your help!
Nicola

Hi Nicola,

Thanks for sharing the details. Some additional questions:

1. what is the integration time (TINT)? It wasn't clear from the waveforms.

2. Are you seeing this issue on 1 device only or multiple devices?

3. Have you also tried in application (non-TEST) mode? Do you see any toggling in the last 4 channels (Ch1-Ch4)?

4. What is the device power consumption both on AVDD and DVDD supplies?

5. Can you share your board schematics?

6. Can you confirm if you follow the power up sequence (See Figure 28 and Table 12 in the datasheet.)?

You had mentioned, "it looks like the working channels are 5,6,7 and 8, so the pinout doesn't corresponds."

I am not able to follow what you mean by "so the pinout doesn't correspond.". Can you please clarify?

Hi Praveen,
1. I've tried both very long integration times (~10 ms) to very short ones (~10 us) to test both continuous and non continous mode, but the results are the same. I have clearly different values in the output stream, but always for 4 channels.
2. I've tried 3 devices, same story. However those were consecutive chips (bought from Digikey) so it might be that they present the same defects.
3. No activity on the DOUT after ~20 us even touching the inputs with my fingers: on the other 4 channels this is introducing a lot of noise (obviously).
4. it is hard to tell for the 5V line since I have the Vref circuitry on the same line (see schematics). What I read is:
3.3V (DVDD) 40mA
5V (AVDD) 140mA when 3.3V not applied, 170mA when 3.3V applied

5. This is a prototype board, so basically I'm only routing out the digital IO to an FPGA, while the analog inputs are coax connectors.

 

6: I have the reset pin that is a switch that I turn on manually after power up. CLK is always present, but I'll test enabling the clock after the reset.

What I mean by "the pinout doesn't correspond" is: the pinout of DDC114 is identical to DDC118, but the inputs that are connected are 1,2,3,4. While I see activities on 5,6,7,8. This is excluding (I think) a mixup in the labeling of the chip.

Many thanks for your efforts in trying to understand this!
Nicola

Hi Nicola,

Thanks for sharing all the information requested. I will need to discuss with the team and shall get back to you by Friday.

Hi Praveen,

Thanks! In the meantime I'll keep investigating. For example I can already confirm that (related to you question 6) even enabling CLK a bit after RESET is not changing the situation.
I do hope I'm missing something obvious!

Thanks and best regards,
Nicola

Hi Nicola,

Checking your board schematics, pins 33 and 34 are connected to GND. The datasheet recommends to leave these pins unconnected. 

Also the current drawn on 5V and 3.3V supplies are too high. Current on the AVDD should only be around 20mA and the DVDD rail should be ~1.5mA. 

Hello Praveen.
Indeed pins 33 and 34 are wrongly connected to GND. Unfortunately it is not an easy fix on our board: we could disconnect both of them from GND, but they are still connected together (and with 35) and the behaviour is the same. In more details, the pins are at 1.5V. This could also explain the increased current drawn.
It will take some time to respin the PCBs and confirm that this was indeed the problem.
Would it be possible to have some documentation about those pins? In particular, is connecting those pins togeter disabling 4 channels? is it an expected behaviour?

Thanks and best regards,
Nicola

Hi Nicola,

Typically the NC pins are internal pins primarily used for testing / debug purposes. Since this is a very old device, I do not have much information about the NC pins.