ADS54J66EVM: JESD204B The deterministic delay

Zhonghui,

The best way to describe this if you had a pulse going into a JESD ADC that then sent the data to a JESD DAC, then you also connected the input pulse to an oscilloscope and also monitored the DAC output on the oscilloscope, every time you cycle power the delay between the pulses will be the same. This is called deterministic latency.

Regards,

Jim

Hi Jim,

Appreciate it.
The reply does make sense, clearly describe the deterministic delay.

Furthermore, when deterministic delay is achived and the phase of ADC input signal is random, the phase of DAC ouput is same or not ?

Best Regards

Zhonghui,

The phase of the DAC will be delayed from the ADC phase by the latency from the link. This latency will be constant.

Regards,

Jim

Hi Jim,

In this case, the delay between DAC phase and ADC phase is deterministic and fixed. If we have the situation that the phase of ADC input is random, the DAC phase can be calculated by adding ADC phase and the delay simply.
The key is can ADC lock the phase of input analog with the ADC device clock, and make the ADC output has a fix phase?

Think you for your help!

Best Regards

Zhonghui,

Did you mean to say "DAC" instead of "ADC" in the last sentence? If so, I think this can be accomplished. If using the NCO option of a DAC, like the DAC38RF82, the device has an option to adjust the phase. You could program this phase to shift the output so that the end result would line up the output to match the phase of the ADC input if the ADC input is synchronized with the device clock. Both the DAC and ADC will be using synchronized device clock and SYSREF inputs. 

Regards,

Jim

Hi Jim,

Think you for your help!

It is useful.

Best Regards