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ADS9120: About SPI Clock

Ryu Yamashita
Genius 3785 points
Part Number: ADS9120


Hi team,

The first page of the data sheet lists the SPI clock as 200 MHz for regular and 45 MHz for enhanced.
However, the Timing Requirements do not list them.
Does this mean that each item in the Timing Requirements is for a method other than SPI?
Also, what is the speed of the internal CLK?
Should I enter the value on page 1 of the datasheet for SCLK to work with SPI?

Sincerely.
Ryu

  • +1
    TI__Mastermind 47090 points

    Hello Ryu,

    We do not specify specific clock frequencies for SCLK since the minimum frequency depends on the communication mode used, such as the number of SDO pins, the frame length, data transfer zone, and SPI or Source-Synch mode.  All of the relevant timing requirements for SPI mode are listed in Section 6.8, along with Section 6.6.

    For 3-wire SPI, you can refer to section 7.5.2 for more details on how to calculate the exact minimum SCLK for your configuration.  As an example, the 45Mhz listed on page 1 assumes using 3-wire SPI (single SDO) and data transfer Zone 2.  The equations used to arrive at this minimum SCLK frequency are equations 8 and 9 in the datasheet.  If you used dual-SDO, then the maximum clock would be 1/2, or roughly 22.5MHz.

    1. There are separate timing specifications for SPI mode (Section 6.8) and Source-Synchronous mode (Sections 6.9 and 6.10)

    2. When using Source-Synchronous mode (Internal Clock), you can set the internal clock to 100MHz (INTCLK), 50MHz (INTCLK/2), or 25MHz (INTCLK/4).  The clock periods are specified in section 6.10, t-STR time period.  When using this mode, the internal clock output is provided on the RVS pin.

    3.  If you use zone 2 data transfer and a single SDO pin in SPI mode, then yes, you can set SCLK=45MHz, which will support 16b data transfer at the maximum 2.5MSPS data rate.  Please refer to Figure 49 for more timing details.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Genius 3785 points

    Hi Keith,

    Thanks for your reply.
    I understood well.
    But let me ask you one question.
    In section 6.8, the maximum value of CLK is 75MHz.
    If I use ZONE1, I think it will exceed 75MHz.
    Is this the MAX value assuming that ZONE2 is used?

    Sincerely.
    Ryu

  • +1 in reply to Ryu Yamashita
    TI__Mastermind 47090 points

    Hello Ryu,

    If you use Zone 1, then the 'theoretical' minimum SCLK needed to clock 16b data at 2.5MSPS will be 200MHz.  However, the maximum allowed SCLK frequency for the ADS9120 is 75MHz, so it is not possible to use Zone 1 data transfer with a single SDO and support 2.5MSPS.  However, you can use quad-SDO (4 SDO pins) which will reduce the minimum SCLK frequency to 45MHz when using Zone 1 data transfer.

    The answer to your specific question is 'no', the 200MHz applies to Zone1 transfer, but the device cannot support any SCLK frequency greater than 75MHz.  If you want to use Zone1 at the maximum data rate, you will need to use the quad-SDO mode.  The other option is to use Zone2, which increases the available time to transfer the data and reduces the minimum SCLK frequency to 45MHz.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Genius 3785 points

    Hi Keith,

    Thanks for your reply.
    I understood well.

    Sincerely.
    Ryu