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ADS8556: Parallel Interfacing with FPGA ; Proper Busy signal obtained. But 400mV random data obtained in Data bus.

Subhash Joshi
Prodigy 10 points
Part Number: ADS8556

Greetings.

I am working on a project to interface ADS8556 in parallel interface with a FPGA using VHDL. I am using a custom FPGA board for this project.

During coding and testing, I got many doubts that i would like to get clarified.

1, The internal clock frequency of ADS 8556 is 36 Mhz. So i programmed FPGA to run in 36 as well as 72 MHz . In both cases,  i got a momentary busy signal only. So I tried 18 MHz and 12 MHz and i got the busy signal(1.2microseconds). So exactly which clock frequency should I use? Does synchronisation matter in parallel interface?

2. Using half or one by third of internal frequency, I programmed FPGA as follows.

a. Reset state for the convst,RD,WR, etc.

b. as shown in updating the CR, I configured the CS and WR signals and placed data 31-16 and 15-00 in data bus.

c. after the read stage is initiated. using CONVST and BUSY. When CONVST is made high and when busy became zero after this state, i made the CS and RD signals low and tried to read data.

The waveforms are attached below.

  

In this waveform, the channel 1 represent the busy signal and channel 2 represent the CONVST signal.

I am trying to read only one channel CH A0 through this code.

So from the busy signal I assumed that ADC is working fine .

But No data is obtained from the ADC. Instead of actual data, i am getting small 400mV pulses in random channels of ADC DB.

  • 0
    TI__Mastermind 24940 points

    Hello,

    1. The busy signal is independent of the clock rate, the conversion time should be 1.26uS in parallel mode, which is indicated by the BUSY pin. I am confused as to what this clock signal is being used for? which pin is this clock connected to, is this pin 27?  note that C10 and C11 of the control register will configure what pin 27 is used for. how are this registered configured?

    2. Would you please include all the digital buss communication to better debug, including CS and RD. from the screen shot provided, that sole interaction looks fine. Please also include the write access to the device, with WR

    I suggest connecting known DC input signal to the ADC channels to debug, this will provided an expected output and can be compared to the actual output

    Regards

    Cynthia 

  • +1 in reply to Cynthia
    Prodigy 10 points

    Thank you Cynthia for the reply. Please let me clarify 

    1. The clock signal is used for the FPGA alone. In some papers which used ADS8556 exclaimed that the FPGA clock frequency must be a multiple of the ADC internal frequency. The clock is not fed into the ADC at all.  The pin 27 is held high at 3.3 V from the FPGA power supply. The ADC must be configured through software mode. The C10 and C11 are both held low. These registers are configured through parallel write access . I hope that ADC got configured,as there is no pin to confirm the configuration successful or not.

    2. I used FPGA  to recreate the timing diagram for both read access and write access.

    Parallel Write Access:

    When Reset is given to FPGA, it initiate the write access for one time only. after that, the FPGA controller goes into read mode.

    The reset to FPGA  initially set the ADC reset pin high for 50ns and then set it low. after that the chip select is set low. and two WR signals are sent along with two sets of 16 bit data during each rising edge of WR.

    this is the two WR signals.

    AS per simulation using modelsim, this signal occurs during CS low. data is placed in the databus during WR falling edge and data is changed during high state in between.

    After this state is over, the FPGA starts the reading process by sending the CONVST signal and the busy signal is obtained. which is already posted above.

    The CS  (channel 2)and RD (channel 1) signal is shown below.

    since I am planning to read only one channel CH A0, I give only one RD signal.

  • 0 in reply to Subhash Joshi
    Prodigy 10 points

    The problem was with the FPGA inout port configuration. When the inout port was properly defined, I got the output. 

    Thank You for the support.