ADS5294: Digital processing data width and 16-bit serialization

Hu Zhan

Part Number: ADS5294

Hi,

What's the internal data width in the calculation of the filter equations on P53 of the datasheet? Since the data and the coefficients are 14-bit and 12-bit wide, respectively, and since there are 24 (<2^5) numbers in the summation, I guess, ADS5294 would need at least 31 bits to prevent the summation from overflowing.

A related question is about the 16-bit serialization, which is mentioned in the datasheet without details. Could you clarify the algorithm that generates 16-bit numbers from the above digital processing? And can I assume that the 16-bit LVDS timing is the same as the 14-bit one except for packing 16 bits instead of 14 bits within a frame clock?

Thanks,

has a digital processing block that can apply FIR filters to the data.

over 4 years ago

0 Abhishek Vishwa1 over 4 years ago

TI__Expert 7140 points

Hi Hu,

Thanks for reaching out.

Let me check the above questions with my team and I will get back to you.

Best regards,
Abhishek

0 Abhishek Vishwa1 over 4 years ago in reply to Abhishek Vishwa1

TI__Expert 7140 points

Hi Hu,

Appreciate your patience.

Just wanted to let you know that I am still working to get this information to you as soon as possible.

As you rightly pointed out that internally ADS5294 will require 31 bits get the output of the filter in order to prevent overflowing, usually we selects the bits according to the gain of the filter.

I still am trying to get the internal implementation of the device and based on that I will be able to answer your question correctly. Kindly allow me some more time to get this information.

I will get back to you latest by Wednesday.

Thanks and regards,

Abhishek

0 Hu Zhan over 4 years ago in reply to Abhishek Vishwa1

Prodigy 10 points

Hi Abhishek,

Thanks for the messages. I'm looking forward to your findings.

Best,
Hu

+1 Abhishek Vishwa1 over 4 years ago in reply to Hu Zhan

TI__Expert 7140 points

Hi Hu,

So I checked the implementation of the filter in the device.

According to the datasheet equation 2; iin order to compute the y[n], we would need 12(coefficient)+14(x[])+ 5(sum), a total of 31 bits.

We then take the signed MSB bits according to the required data bits. So essentially the MSB 14 bits is taken as the final output of the decimation block.

Could you clarify the algorithm that generates 16-bit numbers from the above digital processing? Takes the MSB bits

And can I assume that the 16-bit LVDS timing is the same as the 14-bit one except for packing 16 bits instead of 14 bits within a frame clock? Yes, you are correct.

Thanks & regards,

Abhishek

0 Hu Zhan over 4 years ago in reply to Abhishek Vishwa1

Prodigy 10 points

Thanks for the info!

0 Abhishek Vishwa1 over 4 years ago in reply to Hu Zhan

TI__Expert 7140 points

Thanks for reaching E2E

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ADS5294: Digital processing data width and 16-bit serialization