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DAC5688: Wave glitch on CHA or CHB

Part Number: DAC5688

Hi, Im Juan Camilo.

I have the DAC5688 with this configuration:

Register Address Register Data
0x01 0x09
0x02 0x60
0x03 0x00
0x04 0x00
0x05 0xB0
0x06 0x00
0x07 0x00
0x08 0x00
0x09 0x00
0x0A 0x00
0x0B 0x00
0x0C 0xFF
0x0D 0xFF
0x0F 0x40
0x10 0x00
0x11 0x00
0x12 0x10
0x13 0x10
0x14 0x00
0x15 0x00
0x16 0x00
0x17 0x17
0x18 0x80
0x19 0x00
0x1A 0x0E
0x1B 0xFF
0x1C 0x00
0x1D 0x00
0x1E 0x00

Im doing the steps in the section "RECOMMENDED STARTUP SEQUENCE" and after doing all this, the TXENABLE signal change from low to high. My clk1 is single ended (250 MHz) the CLK2 is differencial clock (500 MHz), the CLK1, DA and DB  are provided by a FPGA and the serial interface, RESET, SYNC and TXENABLE are provided by a PIC.

With the bit2 (inv_inclk) of CONFIG1 I can change the glitch from CH1 to CH2, when this bit is "0" the glitch is in CH2 and when is "1" the glitch change to CH1. I would like to know if I have the correct configuration on DAC5688 or I need to modify some registers.

Regards,

Juan Camilo Peña A.

  • Hi Juan,

    I am waiting for the evaluation module for this device to show up at our lab. Once I receive this (5-7 days), I will run your configuration on our hardware and let you know of the results. In the meantime, could you upload an image of this "glitch" so I can better understand what exactly you are seeing? Also, is this something you are seeing on a single device or is this across numerous devices? Welcome to E2E.

    Thanks, Chase

  • Thank you for your anwser Chase.

    To detect the glitch with more visibility we are using ramp signals, frequency = 500 KHz. The amplitude doesnt matter because the glitches always appear in the same places. You said "Also, is this something you are seeing on a single device or is this across numerous devices" To answer your question, we are testing on 3 different boards (devices) with the same hardware and each of one give us the same result

    This is the DAC outputs with CONFIG1 = 0x0D. (DA = green ; DB = yellow)

    This is the DAC DB output with CONFIG1 = 0x09, the glitch is more visible.

    To add more information about the clocks, the CLK2 has a LVDS 3.3V format and the CLK1 has LVCMOS 3.3V

  • I had made a mistake with the following registers, these are the actual values

    Register Address Register Data
    0x0E 0xDF
    0x17 0x05
  • Hi Chase,

    Do you have any update for me ?

    Regards,

    Juan Camilo Peña A.

  • Hi Juan,

    Sincerest apologies for the delay. We have received an EVM and I have it set up with the configuration you have described. I will start testing first thing on Monday and get back to you with the results.

    Best,

    Luke Allen

  • Hello Juan,

    I have taken some measurements using the DAC5688 EVM with the clocking setup you have described above.

    • Clk1 - Single Ended, 250MHz
    • Clk2 - Differential, 500MHz 

    I generated a 1MHz sine wave and sent it to the DAC using HSDC Pro and I am not seeing any glitching like you have described. Shown below is the outputs I measured, output channel A is shown in yellow and output channel B is shown in orange. Additionally, changing this inv_inclk bit has no effect on the output signals.

    It could be possible that for your application, some other aspect of the design is affecting the output. Below I have included the register config file that I used for your reference.

    Texas Instruments Inc.
    DAC5688 EVM Register Configuration
    
    DAC5688 Registers
    Address	Data
    00		01
    01		09
    02		20
    03		00
    04		19
    05		10
    06		00
    07		00
    08		00
    09		00
    0A		00
    0B		20
    0C		A6
    0D		A6
    0E		00
    0F		2D
    10		00
    11		00
    12		00
    13		00
    14		00
    15		00
    16		AA
    17		10
    18		80
    19		00
    1A		0E
    1B		FF
    1C		00
    1D		00
    1E		00
    
    CDCM7005 Registers
    Address	Data
    00		005FF1F0
    01		029002DD
    02		D04800A2
    03		00000027
    

  • Hi Juan,

    Please let me know if this register configuration works better on your end. If not, we could possibly take a look at the schematic for your design and determine if there may be something causing an issue there.

    Best,

    Luke Allen 

  • Hi Luke,

    We tested your register configuration and the result still the same. The yellow signal is CHA and green signal is CHB.

    This is our DAC schematic. To test the single mode (CLK1) we removed C226 and R234 so the pin (CLK0/CLK1) is floating. Additionally the C230 value is 1nF.

    Regards,

    Juan Camilo Peña A.

  • Juan,

    Are those measurements taken directly form the output pin of the DAC? Do you have some circuitry at the output of the DAC? If  so, could you share that schematic as well?

    Best,

    Luke Allen

  • Hi Luke, this is the output taken of DAC pins, the previous images showed signals with higher amplitude because of the HW after the DAC.

    The yellow signal is IOUTA1, green signal es IOUTA2 and purple is (IOUTA1 - IOUTA2) 

    The yellow signal is IOUTB2, green signal es IOUTB1 and purple is (IOUTB2 - IOUTB1) 

    We are seeing the glitch on output A. Can you say to us if any thing is wrong on DAC schematic? 


    Thanks,

    Juan Camilo Peña A.

  • Hi Juan,

    I see no issues with the portion of the schematic you sent me. I am thinking something else on your board may be causing this. Lets try to get a sine wave working first. If you try outputting a sine wave and increasing/decreasing the frequency, how does the glitch change? If you connect the output to a spectrum analyzer when outputting a sine wave, do you see any spurs that are not harmonics? This could help us determine if the glitch is being caused by another signal combining with the output signal of the DAC.

    Best,

    Luke Allen