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AFE7222: Test patterns synchronization, DDR sample output sequence

Mike Neuman
Prodigy 140 points
Part Number: AFE7222

I'm using the AFE7222 in CMOS mode. 

Are the test patterns on the two channels synchronized in any way (or is there a way to get them synchronized)? If I put both into TOGGLE mode, I'd like both channels to read 555 or AAA at the same time. If I put them into RAMP mode, I'd like them to roll over at the same time to the next value.

Also, to clarify, in CMOS DDR mode, let's say sample 0 is taken by ADC A and B on a single clock edge, giving two samples A0 and B0 (followed by A1/B1, A2/B2, etc). Will A0 be driven on the rising edge BEFORE B0 on the next falling edge? Or will B0 be on the falling edge immediately preceding A0? 

In other words, will the sequence look like:

B0 A0 B1 A1 B2 A2

or

xx A0 B0 A1 B1 A2 B2

Thanks!

  • 0
    TI__Genius 11930 points

    Hi Mike,

    The test patterns on the two channels are asynchronous and the AFE does not have the capability to synchronize them.

    In CMOS DDR mode the sequence should look like the following: A0 B0 A1 B1 A2 B2

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 140 points

    Understood on the test pattern.

    Are you certain about the DDR sequence? With a variety of experiments, it really appears as though I'm receiving B0 A0 B1 A1... It's possible my experiment conditions are wrong, but I've tried looking at this from a variety of angles.

    Thanks!

  • 0 in reply to Mike Neuman
    TI__Genius 11930 points

    Hi Mike,

    The DDR sequence should be A then B. Section 10.1 of the AFE7222 datasheet goes over this sequence.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 140 points

    The documentation on that page is vague at best. "A then B" could simply be a definition of what interleaved means. The diagram then shows B preceding A. Although it does show centered clocks on an A then B combo.

    I have 2 pieces of evidence which seem to counter this:

    1) The very first sample received from the AFE with a RAMP value is on the negative edge (i.e. "B0"?)

    2) When provided with a sine wave, I and Q only align properly if B precedes A.

    If you're certain that B follows A, then I don't know how to explain these two datapoints but will continue my hunt. If you're just interpreting a fairly vague passage from the manual with no additional data, please let me know that as well.

    Thanks again!

  • 0 in reply to Mike Neuman
    TI__Genius 11930 points

    Mike,

    As this is an older part and I do not have an EVM to test, I am referring to the datasheet for my answer.

    I will check with my team to see if there is any additional information available on this part.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 140 points

    Thanks, David. I appreciate it!

  • 0
    Prodigy 140 points

    Just a ping to see if you have had any progress, David. I've made my way to the DAC and it seems to be have the same setup as the ADC (B on falling edge precedes A on rising edge for a single time slot). If confirmation is possible, I'd appreciate it--otherwise I'm repeating the same bug over and over. :-)

  • 0 in reply to Mike Neuman
    TI__Genius 11930 points

    Hi Mike,

    I have received no new information from my team at this moment, but we are working on contacting one of the parts designers for more information.

    Regards,

    David Chaparro