ADC12DJ3200EVM: KCU105 FPGA design for ADC12DJ3200EVN

Hi Harry,

I was able to upgrade the project to version 2020.2 of Vivado and the upgraded files can be downloaded using the link below. Please note that this reference design was created by a 3rd party, who no longer supports firmware, so we can only provide minimal help with any issues regarding this project.

https://tidrive.ext.ti.com/u/_ojtJG0I7RbsiO0j/036b170d-49da-47bd-91ab-c6b394324734?l 

For more in depth assistance I would recommend using TI's TI204c-IP: https://www.ti.com/tool/TI-JESD204-IP 

Regards,

David Chaparro 

Hi David,  Do you know if this works in the hardware?  I was able to upgrade the files too but my project doesn't work in hardware.

Hi Harry,

I only attempted to upgrade the project because I did not have the hardware to test. Are you receiving any errors when testing updated project?

Regards,

David Chaparro

I can't get data to flow through the design.  I have a KCU105 and the ADC.  However, when i run through all the steps to set up the design, download the bit file and configure the ADC I get no data, frame sync is always low, but the clocks are locked.

I have a design that i created which essentially is configured exactly the same as the example and I get the same results.  I know that according to Xilinx when using subclass0 you don't need to use the sysref, so i don't use that in my design.

I'll download your design today and give it a shot and let you know.

I just downloaded the design and can't get it to work. I get all 0's pretty much everywhere except i get a flashing light on the KCU105.