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ADS54J69: JESD and DDC questions

Part Number: ADS54J69


Hello,

One customer used ADS54J69 and met questions as following:

1. Configure the ADC with 4222 mode, Reg 0x52=0x08,0x72=0x08. According to Figre74, it should output from Lane0 and Lane1. But actually, lane 1, lane2 and lane 3 all have data output, and Lane1 and Lane3 output the same data. If 0x52=0x00, 0x72=0x00, this time only lane2 and lane have data output. So the channel output is inconsistent with the datasheet.

2. The sampling clock input is 500Mhz, and also used 4222 mode,  2x FIR extraction, if input 10M single tone signal, the result is a spectrum with many harmonics, And the higher the frequency, the more harmonics, what could be the cause?

Best regards

Kailyn 

  • Hi Kailyn,

    1) The correct register writes to address 0x52 is 0x80 and address 0x72 is 0x80 (not 0x08). 

    2) Ensure that the input tone is being filtered to address the issue with the harmonics. 

    If issues continue, please send along the configuration file so we can double check the register writes.

    Regards, Amy