Part Number: ADS42LB69
Hi team,
Input external clock sampling rate 204.8M, at input signal 0DBM, center frequency 153.7M, band pass filter added to the outside of the signal, spectrum is basically normal, The spur is very small and basically conforms to the characteristics of the device. However, when the input signal reaches -22~-40dbM, the spur on both sides of the signal increases and does not decrease as the signal input amplitude decreases. See the yellow text in the figure below. The problem has been found on several different boards, and the main question now is why when the signal input amplitude decreases, the clutter on both sides increases. We suspect this is a problem with the ADC itself sampling. The problem with the signal source and the clock can be eliminated. The second figure is our front-end circuit.


Best Regards,
Amy Luo
