ADS8665: Can someone please advise how to know if the ads8665 is booting correctly?

Hi Edmond,

There are no more diagnostic features on this ADC. To check if your register writing works, you can read the written register content back to compare. Also, you can read any register after power up, then you can compare the reading data with the default data. 

The default configuration for the /RST pin is power-on reset after the device is powered up. The ADC should enter ACQ state and the RVS should go high after a delay pf tD_RST_POR according to the data sheet. What's the width of your RESET signal low (high-low-high)? What's the status of your /CONVST/~CS and SCLK when your /RST pin is pulled to high? A  timing graph will be better to check. Thanks.

Regards,

Dale

Hello Dale,

Thank you for your prompt reply.

The RST/ pin, Cs/ pin, and Sclk pin all were pulled Low before starting the main spi section of code.

Only the Rst/ pin was pulled High, then wait up to 100 msec.  No Rvs High has been observed.

Moving the CS/ to High causes the RVS to go High straight away, although I have not tested 

at 10 nsec.

So,,,,,   Is the RVS supposed to go High independently of CS/ at 20 msec or so to confirm boot?

What is the interpretation if this does not happen?

Reading any of the registers using Spi responds the register command left shifted one bit.

Reading the Adc with a 0x00000000 spi prompt returns either 0x000 or 0xfff in the left 

most bits, then 0xfffff.  I infer from this that maybe Vref not connected.

Spi Clock polarity starts Low.

Spi Phase is first edge

The cpu is stm32 f767.  This cpu stimulates 16 bits at a time.   Thus there are two 

interrupt driven writes and two interrupt driven reads each transaction.  The result is 

broken into words to make interpretation easier.

Because there are no intermediate Adc values, my concern is that the device has not 

booted, is the Vref indeterminant??

Thank you for your time and consideration.

Best Regards,

edmond burzycki

Hi edmond,

The RVS signal is related to the /CS signal which is same as the CONVST. When the /CS is high, the RVS reflects the status of the internal ADCST signal. For example, after tconv time from the rising edge of CONVST/CS, the RVS will go from low to high as the ADCST internal signal which indicates that the internal conversion has been completed and the data is ready for the microcontroller to read. When the /CS is low, the status of RVS depends on the output protocol selection. When the CONVST/CS is pulled low by the microcontroller to initiate a data transfer, the RVS will go low for indicating the beginning of the data transfer frame.

No signal is intended to monitor the device, indicate and confirm the device boot. The RVS signal is mainly used to retrieve the conversion data by monitoring a low-to-high transition on the RVS after the CONVST/CS is issued to start a conversion. Another way to read the data is to wait for the tconv_max time instead of monitoring the RVS signal.

You SPI configuration (polarity low and first edge phase) is correct if you did not change the default SPI configuration on the ADC (CPOL:CPHASE=00). By default, the internal voltage reference is enabled after power up. 

Did you measure the voltage on the REFIO pin? Can you reset the device with a high-low-high pulse instead of low-high? Your timing plots and schematic are helpful to address the issue.

Regards,

Dale