ADS8671: The amplitude of the signal acquired is reduced by 4.5-5.5 times

Hi Kailyn,

What's the code you got? What's the voltage on the ADC input (amplifier output) for the code? I need more information to address the issue. A schematic will be helpful. Thanks.

Best regards,

Dale

Hi Dale,

Thank you very much for your reply. ADC input is +-12.288V for the code， and the schematic is as following。

In addition, the customer didn't reply me about the detailed output code.

Best regards

kailyn

Hi Kailyn,

Thank you for providing more information. Is the DGND shorted to the AGND? I can not see that in the schematic. Can you please ask the customer to measure the voltage on the REFIO and REFCAP pin? Also, can you provide a closer timing plot captured with an oscilloscope for SCLKS, /CS,SDO and SDI for the +/-12.288V input? Notice that the +/-12.288V are the maximum/minimum voltage range, Please confirm if these voltage were measured on the ADC's input, not at other location. Thanks.

Regards,

Dale

Hi Dali,

Thank you for your reply. REFIO=REFCAP =4.096V, ADC input is +-12.288V which measured on ADC's input. SCLK=100MHz.

The conversion results are 11100111100001, he writes the SDI always zero because he only need ADC output.

Best regards

Kailyn 

Hi Kailyn,

The maximum SCLK which can be used for the ADS8671 is 66.67MHz, see the timing requirement in the table 6.8 in the ADS8671 data sheet. Your 100MHz SCLK is too high for this ADC. Please reduce it and check again.

Also, your timing does not help because it's hard to see. Below is a closer timing example which was captured with a logic analyzer.

Best regards,

Dale

Hi，

The waveforms are as following:

REFIO

REFCAP

(CS)

(SCLK)

(SCLK)

(No AIN_P input, SDO output)

AIN_P input

SDO output with AIN_P input 

Best regards

Kailyn 

Hi Kailyn,

Did you reduce your SCLK frequency and check again? 

Also, your SCLK is showing an obvious interference signal which can lead to an incorrect reading, you have to figure out where it comes from and remove it.

Your reference voltage is correct even it's not very accurate because you are using an oscilloscope to check.

Seeing code on the SDO for no AIN_P input is normal because the ADC will output the internal bias voltage when the AIN_P is floating. Once a signal is connected to the AIN_P input, the ADC will output the conversion code for the analog input.

It's hard to check if your SDO output is correct with an available AIN_P input because the timing for SDO and SCLK are shown in different graph. Can you capture the SDO,SCLK,/CS and SDI in a same timing? A DC input lower than 12V will be good for test purpose because 12.3V is beyond the maximum input range.

Best regards,

Dale