AFE5816: Data converters forum

Hello,

Thanks for sharing your concern.

Can you please elaborate more on the exact problem? Are you facing difficulty in HOLD_GAIN_TIME setting only?

In general, the internal non-uniform mode - profile registers and memory bank has to be programmed. Are you able to correctly program the same? You can read back and verify this as a first step. (you may follow the spi readout section). 

To program register settings in the DTGC register map, set the DTGC_WR_EN bit to 1. Are you taking care of the DTGC_WR_EN bit?

Please share some more information about your issue and meanwhile I will look at the details of the implementation.

Thanks & regards,

Abhishek

Hi,
I'm sorry for lack of explanation.
The following register settings are made and it is confirmed that there seems to be no problem in operation.
ADD:0x00/DAT:0x10,
ADD:0xB5/DAT:0x13F,
ADD:0xB6/DAT:0xCF80,
ADD:0xA1/DAT:0x9F,
ADD:0xA2/DAT:0x101,
ADD:0xA3/DAT:0x50,
ADD:0xA4/DAT:0x64,
ADD:0xA5/DAT:0x1300,
ADD:0xB9/DAT:0xC0C0,
ADD:0xBA/DAT:0xC0C0,
ADD:0x01/DAT:0x404,
  :
ADD:0x50/DAT:0x7F,
ADD:0x51/DAT:0x0,
  :
ADD:0xA0/DAT:0x0

When I changed "HOLD_GAIN_TIME_0" from here, a problem occurred.

Best Regards,

Hi,

Thanks for sharing the information.

I'll review it and consult my team regarding this and get back to you by tomorrow.

By the way, what is the problem that is happening? Could you explain the phenomenon.

Is it getting stuck? Or is the gain stays for more than the applied time? etc.

Thanks & regards,
Abhishek

Hi,
Change "HOLD_GAIN_TIME_0" to the state shown in Fig. 1.
The changes are as follows:
ADD:0x00/DAT:0x10,
ADD:0xA5/DAT:0xD80,

The expected result is Figure 2.
Brightness: No change = No gain change
Gain area: Equivalent to 0xD80

However, the result is shown in Figure 3.
Brightness: Darker = Gain decreases
Gain area: No change

Best Regards,

Hello,

Firstly, to clarify the HOLD_GAIN_TIME_0 is the STOP_GAIN_TIME which is illustrated in the figure 69 (Internal Non-Uniform Mode). 

From your programming sequence you are setting it to 4864 ADC clk cycles and modifying it to 3456 clk cycles will take effect in the next TGC_SLOPE signal.

From the sequence you shared, I see that it is correct. I dont see any problem with the sequence. I have included some comments about the settings which you can verify.

ADD:0x00/DAT:0x10,                   Enable DTGC programming
ADD:0xB5/DAT:0x13F,                 Slope_fac[0] = 0; en_int_start =0; mem bank = 0; manual start = 0; manual_gain_dtgc = 319
ADD:0xB6/DAT:0xCF80,              slope_fac = 0; Profile 0 selected; internal non uniform mode; input resistance = open; attenuator enabled.
ADD:0xA1/DAT:0x9F,                   start_gain_0 = 0; stop_gain_0 = 159
ADD:0xA2/DAT:0x101,                 pos_step_0 =1; neg_step_0 = 1
ADD:0xA3/DAT:0x50,                   start_index_0 = 0; stop_index_0 = 80
ADD:0xA4/DAT:0x64,                  start_gain_time_0 = 100
ADD:0xA5/DAT:0x1300,              hold_gain_time/stop_gain_time = 4864
ADD:0xB9/DAT:0xC0C0,             // Since profile 1 is not used, can C000; fixed attenuation : 0dB
ADD:0xBA/DAT:0xC0C0,            Not needed
ADD:0x01/DAT:0x404, 

ADD:0x50/DAT:0x7F,

ADD:0x51/DAT:0x0,

Further, let me share this data with my team and see if they can figure out why this is happening.

I will again get back to you either by tomorrow or early next week.

Thanks & regards,

Abhishek

Hello,

I shared the image with my team. So there is some in information we require to fully understand what is happening.

In the image, can you share the time information with depth on the -y axis. We need the timing information in terms of us from the point where TGC is started and internal non uniform mode starts.

Thanks & regards,

Abhishek

Hi,
The repeat time in the depth direction is 136us.
wait to start stage = 2us (start_gain_time_0 = 100)
Ramp stage = 40us
Wait to Stop Stage = 97.28us (hold_gain_time/stop_gain_time = 4864)

Best Regards,

Hi,

Thanks for this. 

The timing is okay. I need to see the depth on the graph. Can you mark it? for example the green colored indicators are there on the image on the right side. can you mark these numbers.

Thanks & regards,
Abhishek

Hi,
It is a gain curve image up to a depth of around 30 mm.
After this, the Ramp stage is executed.
Is this not enough?

Best Regards,

Hello,

I think the problem is related to not waiting for the Gain to come back to the start gain after the HOLD_GAIN_TIME_0. According to your settings, you have set NEG_STEP to 1, which means that there should be another 160 ADC clock cycles for the GAIN to come down to 0 from 159. 

Can you program NEG_STEP_0 to 159 so that you come back to start gain in 2 ADC clock cycles? Once you do this can you share the final image.

Thanks & regards,
Abhishek

Hello,

Just checking since I did not hear back from you. 

Are you able to resolve the issue or is it still persisting? Did you try changing the NEG_STEP value.

Also, can you also try increasing the repeat time to > 140us

Regards,
Abhishek

Hi,
Sorry for the late reply.
I tried changing NEG_STEP, but the phenomenon did not change.
Changes could take effect after several accesses to TGC-related registers, including HOLD_GAIN_TIME_0.
It may be because the settings are not correct, but it seems that the registers are not being written properly. (even though I wrote 1 to DTGC_WR_EN)
(For reference, the SPI clock frequency is 12.5MHz. The data is center-aligned output.)
For that reason, it seems that HOLD_GAIN_TIME_0 sometimes operates at the time including the Ramp stage, and sometimes it operates at the time after the Ramp stage according to the data sheet

Best Regards,

Hi,

Its unusual that write is not happening correctly. Do you have a provision to reduce the SPI speed? The device supports up to 20 MHz, so 12.5 should work.

But understand the issue better could you reduce the SPI speed and check if you are facing the issue.

Regards,

Abhishek

Hi,

I wanted to check with you if your issue is resolved with using lower SPI speed?

Were you able to do the reduction if SPI speed?

Regards,

Abhishek

Hi,
Sorry for the late reply.
I set the SPI clock frequency to 8.33MHz, but nothing changed.

Best Regards,

Hello,

I am sorry to hear that it is still not working.

I think next step could be to set up AFE5816 in my lab with your settings and verify whether the problem occurs or not.

Can you send me your config files (complete) to abhishek.vishwa27@ti.com and I will try to replicate your setup at my end.

Thanks & regards,

Abhishek