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Original question:

ADS5263: bitwise mode in ads5263

ADS5263: bitwise mode in ads5263

Mohith RS
Prodigy 25 points
Part Number: ADS5263

Hi Abhishek,

As you told it was capture issue we could solve it, thank you for your pointers.

Now, we're facing some more hiccups we're able to see sine wave in ila till 30 MHz sampling clock frequency from 40 MHz output is not coming properly, after this observation we tried to check the same by generating ramp test pattern  using spi registers (0x25,0x0040) even the ramp signal was not coming good from 40 MHz we've to do our system till 100 MHz, Your suggestions on this will be really help full.

i'm attaching the snips of ila outputs too for your reference.

ramp for 30 MHz sampling frequency 

ramp for 40 MHz sampling frequency 

1 MHz input analog signal 30 MHz sampling frequency

1 MHz input analog signal 40 MHz sampling frequency

we have used Xilinx IDDR to capture the samples 

  • 0
    TI__Expert 6790 points

    Hi Mohith,

    From the data you shared, since it is working at lower frequency which implies that the functionality is correct. 

    Now as you increase the frequency, you are seeing timing violations coming into picture and I think most likely it is due to length mismatch while routing the LVDS interface lines.

    In order to solve this issue you will have to invoke the delay blocks in the FPGA IP (most likely it is called idelay). You can vary the delay to adjust for the timing mismatch and verify it is indeed the case.

    Can you share the FPGA architecture information.

    Also, I would recommend you to send the mail on the support_us_afe_tx@list.ti.com and we can continue the discussion there, if you dont want to share information related to your architecture on the public forum.

    Thanks & regards,

    Abhishek

  • 0 in reply to Abhishek Vishwa1
    Prodigy 25 points

    Hi Abhishek,

    We're using Xilinx 7 series FPGA also I have sent a mail on the above given mail ID  please look into it.

    Thanks and Reagrds 

    Mohith RS

  • 0 in reply to Mohith RS
    TI__Expert 6790 points

    Hi Mohith,

    I saw your mail and replied to that on the thread.

    I would recommend you to modify your LVDS data deserialization architecture to allow for correction of any mismatch in arrival time of data and clocks.

    We also use similar technique only. You will get lot of resources/literature available on the web to implement the same.

    I am closing this thread for now and we can still continue on the mail thread to discuss it further.

    Also feel free to reopen the thread if you find any need.

    Thanks & regards,

    Abhishek