ADC081S021: Affect of sample abort on throughput?

Hello Aaron, 

Looking at the timing diagrams in the datasheet, one may be able to collect this data

CS has to have a minimum high pulse of 10ns. When CS is brought high the SDATA is instantaneously set to tri-state. Note, this can be in parallel to the Tquiet time of 350n, but both these requirements are independent and both must be met for the next conversion. 

The acquisition time is set specifically by the SCLK, not CS, and from the timing diagram, if CS if high the SCLK are still valid, even if SDATA is in tri-state. thus one can infer that acquisition phase will not start, if aborted, until the clock pulse requirement is met 

Hi, Cynthia - Thank you.  The Throughput section describes a 16-cycle frame at 1MHz.  The specific timing of the rising edge of /CS is not a part of the formulation at all, however because the word "abort" is not mentioned, one might assume that the rising edge occurs after the 16th falling edge of SCLK, and therefore that the /CS pulse width must be less than half an SCLK cycle.  Since half an SCLK at 1MHz is 500ns, which is larger than both Tquiet and Tacq, it can work.  If raising /CS prior to the 16th falling edge of SCLK, while continuing clocking, simply tri-states SDATA before it would normally go tri-state on its own, then everything would still work, and /CS could be raised at any point after all actual data bits are output without breaking the 16-cycle frame timing.  I'd like to *think* this is the case, however the datasheet just isn't explicit about what abort actually means.  If one aborts and does not keep clocking while idle, the behavior would seem to be even less clear, although that's not a scenario that's relevant to me.