ADS54J69: ADS54J69 rxtvalid(adc data valid signal) does not assert high when adc is programmed.

Ismihan Gül Gürbüz

Part Number: ADS54J69

Hi,

I'm trying to run the ADS54J69 in 2242 mode. But when I checked the jesd interface before programming the IC, I saw that the sync pin was constantly dropping. I connected gt_rx output ports of jesd204_phy ip and rx_sync output port of jesd204c ip to ILA to control the interface. You can see the ILA signals in the link below.

https://drive.google.com/file/d/1w1p4Aho0rXOFXa1VBDct8O40oVJKuxI4/view?usp=sharing

After programming the IC (after setting its registers), the adc data is not valid at all. The rx_tvalid (adc1_data_v) signal is always 0. I can not get data from ADS54J69. You can see the ILA signals after programming the IC from the link below.

https://drive.google.com/file/d/1ksrOjkzABmbQdEHM21rfCxLO4knk-68H/view?usp=sharing

Line Rate = 5Gbps

Reference Clock = 125 MHz

I configured the registers of ADS54J69 as follows:

600001

600000

000081

000080

005920

400100

400200

400468

400300

60F701

600001

600000

400469

400300

600080

60060F

600580

600102

60310A

60320A

40046A

400300

601602

601B08

601A02

400468

400300

604112

604D08

605280

607208

600001

600000

Why is the sync signal constantly dropping? Why is the data valid signal not high after programming the IC? Can you help me?

over 4 years ago

0 Amy over 4 years ago

TI__Genius 15321 points

Hi Ismihan,

I am checking into your question and will get back to you soon.

Regards, Amy

0 Drew Pierpont over 4 years ago

TI__Intellectual 1180 points

Hi Ismihan,

Would you be able to post your data as images or a zip file? We prefer to avoid opening links to file share sites like Google Drive. This would help us assist you a little better.

Thanks,

Drew

0 Ismihan Gül Gürbüz over 4 years ago in reply to Drew Pierpont

Prodigy 30 points

Before programming the IC

After programming the IC

+1 Chase W over 4 years ago in reply to Ismihan Gül Gürbüz

TI__Mastermind 24550 points

Hi Ismihan,

Certainly, we can help. Are you following the initialization sequence in the datasheet (page 64)? bcbcbcbc is indicating the K28.5 sequence, which confirms the mapping from the ADC to the FPGA is ok. Something you can try is run the ADC in a mode at half of the serdes speed (reduce the clock to half). This may help to rule out any signal integrity issues. SYNC is an input to the ADC, the FPGA must pull this high. What happens if you map the SYNC to a VIO and toggle this high? Can you show us the ILA data for this?

Thanks

0 Ismihan Gül Gürbüz over 4 years ago in reply to Chase W

Prodigy 30 points

Hello,

We realized that this problem was caused by the clock we gave to the FPGA.

Thank you

0 Chase W over 4 years ago in reply to Ismihan Gül Gürbüz

TI__Mastermind 24550 points

Hi Ismihan,

Thanks for the update. We are glad to hear you resolved this.

Thanks, Chase

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ADS54J69: ADS54J69 rxtvalid(adc data valid signal) does not assert high when adc is programmed.