DAC3171 Alarm clocks

Alessandro Feriani

Part Number: DAC3171

we are going to use the Dac3171 ( 7 bit interface version ) in a project but unfortunately we have some problem to make it workinng.

Basically we have alarms on the Data and Dac clock and we do not understand what the problem could be.

Here below the DATA clk ( LVDS ) and the signals comes from directly FPGA and no external 100Ohm is mounted ( use internal DAC resistor )

Here below the DAC clk ( LPECL20 )

Here below the configuration register applied

SetTxEn(false);
for (UINT32 lToggle = 0; lToggle < 100; lToggle++)
SetReset(true), mSleep(1), SetReset(false), mSleep(1);

//Deassert reset and enbable TX
SetPowerDown(false);
SetSleep(false);
SetReset(false);
SetTxEn(true);

WriteConfig(CONFIG_00_REG, 0x42FC);

SPIRead16(CONFIG_06_REG, & wData); => read 0x4610 (from datasheet is Dac3171)

WriteConfig(CONFIG_01_REG, 0x600E);
WriteConfig(CONFIG_02_REG, 0x3F80);
WriteConfig(CONFIG_03_REG, 0x0001);

WriteConfig(0x05, 0x0000, true);
SPIRead16(0x05, & wData); => read 0xFFC0 sometimes 0xFF40, 0xFF80 and even if I write to zero to clear, i always read out alarms

I can set the output voltage by SPI but not by FPGA.

Any idea?

over 3 years ago

0 Miguel Lomeli over 3 years ago

TI__Intellectual 1950 points

Hi Alessandro,

Is the FPGA providing both DACCLK and DACLK to DAC?

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

Hi thanks for your reply

we use LMK04821NKDT device.

The LMK04821NKDT generates

- LVPECL20 clock for DA_CLK

- LVDS clock for FPGA and the internal logic generates the LVDS DATA clock for DAC ( same frequency )

the oscilloscope picture in the first post show the signal measured near the DAC pins

I hope now it's more clear

Thanks in advance

0 Alessandro Feriani over 3 years ago in reply to Alessandro Feriani

Prodigy 30 points

I measured also the all power supply stability and it seems to me they are absolutely stable.

Any idea?

0 Alessandro Feriani over 3 years ago in reply to Alessandro Feriani

Prodigy 30 points

I measured also the all power supply stability and it seems to me they are absolutely stable.

Another strange thing is related to the LVDS clock signal ( before and after FPGA ).

The signal comes from LMK

and internal IP replicates the LVDS clock for the DAC.

The levels are different

the second could be right for DAC3171?

Any idea?

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

HI Alessandro,

Let me look into this.

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

I tried to wire the 24/25 dataclk input pins and the clock alarms disappear.

So we suppose the mounted IC type is 14-bit version instead of 7-bit even if I set the "dual_ena" bit at config3 register.

Any idea to clarify this issue? is there any register to understand the version type - maybe the confgi127 give me some extrainfo?

thanks in advance

0 Alessandro Feriani over 3 years ago in reply to Alessandro Feriani

Prodigy 30 points

I thins the issue is related to bad configuration 7 vs 14 bit interface mode.

The marking code of the device is

DAC3171I
TI 88J
P11F G4

which version is ?

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

Hi Alessandro,

I just received the EVM, i'll work on trying to duplicate your issue on my setup and see what i can find.

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

Because we need to use the IC 7-bit version type,
what is the right register configuraion to make sure the IC is properly configured?

I hope you can reply soon beucase we are struggling to make it working

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

Hi Alessandro,

After initial testing in 7Bit mode(200MSPS), i don't get alarms enabled when I use the pin 24/25 dataclk. the register writes i did are below as follows.

Reset

0x00 0x4EC
0x01 0x401E
0x02 0x3F80
0x03 0x1C70
0x08 0x6000
0x09 0x8000
0x0A 0xF080
0x14 0x0000
0x01 0x401E
0x01 0x403E
0x01 0x401E

Can you use pin 24/25 instead of sync?

Next i'll look at the sync pins for dataclk instead.

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

Hello thanks for your precious feedback.

We can not use the 24/25 pins because the board has been designed to use 6/7 for dataclk as the pciture below shown.

I hope we can find the solution

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

HI Alessandro,

while i work with the sync pins as clock in the meantime can you try following register writes...

Reset

0x00 0x42EC
0x01 0x401E
0x02 0x3F80
0x03 0x1C71
0x08 0x6000
0x09 0x8000
0x0A 0xF080
0x14 0x0000
0x01 0x401E
0x01 0x403E
0x01 0x401E

For register 0x3, I have clock delays(clkdlya & clkdlyb) added, can you try adding/remove delay time and see if that clears the alarm.

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

yes indeed, adding clkdlya & clkdlyb clear the alarms related the FIFO.

Now remains the data_clok_gone alarm.

Great job Miguel, we are near the solution i hope

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

Do you see an output when the registers above were used? Can you increase the amplitude of the data clock and see if it clears the alarm? Did you also try different variations of clk delays?

Can you adjust the datadly, please reference the datasheet section 6.8 LVDS Input Timing.

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

I did this
I can see DAC output voltages but:

| TI code | MY Code
-------|--------- |----------------------------
0x00 | 0x42EC | 0x42FC ( SIF4_ENA = 1 )
0x01 | 0x401E | 0x401E
0x02 | 0x3F80 | 0x3F80
0x03 | 0x1C71 | 0x1C71
0x08 | 0x6000 | 0x6000
0x09 | 0x8000 | 0x8000
0x0A | 0xF080 | 0xF080
0x14 | 0x0000 | ------
0x01 | 0x401E | 0x401E
0x01 | 0x403E | 0x403E
0x01 | 0x401E | 0x401E

*********************************************
Case 1
*********************************************
0x07 | 0x0740 ( only fifob + dataclk at 1 )

Now I start to clear config5 reg for N times.
0x05 | 0x0000 Write and read this register to clear alarms and check again

I read always alarm_dataclk_gone bit at 1
The others are always zero
=====> the alarm led is OFF !!!!!!

*********************************************
Case 2
*********************************************
0x07 | 0x0040 ( only dataclk at 1 )

Now I start to clear config5 reg for N times.
0x05 | 0x0000 Write and read this register to clear alarms and check again

I read always alarm_dataclk_gone bit at 1
The others are always zero
=====> the alarm led is ON !!!!!!

I tried to loop dataDly from 0 to 7 ( reg 0x03 ) but without any improvment

1) what is the fifoa and fifob, it's not clear from the doc.
2) what is the reg configuration to use DataClk on pin 6-7?

Please help us becuase we are still have alarms

0 Alessandro Feriani over 3 years ago in reply to Alessandro Feriani

Prodigy 30 points

Any Updated? I am still in stuck with this issue and I do not how to fix it

Please help

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

HI Alessandro,

Sorry for the delay, i was on vacation last week. My current board doesn't use sync pins for dataclock. i'm waiting for the modified board to come in.

0 Miguel Lomeli over 3 years ago in reply to Miguel Lomeli

TI__Intellectual 1950 points

Hi Alessandro,

The A|B naming is referring to the two DAC's that are in the device. FIFOA -->DACA & FIFOB -->DACB.

When i try the same config file that i gave you previously my result is no alarms for dataclk. I see that your reg zero is different can you please try 0xEC instead of 0x42FC

0 Alessandro Feriani over 3 years ago in reply to Miguel Lomeli

Prodigy 30 points

Hi, I can not apply your suggestion becuase i need to readout from SPI 4 wire, that's why I add SIF4_ENA = 1 in the first reg

did you recevie your board modified to use sync-pin for dataclock? Please let me know becaue the alarm did not disappear

0 Miguel Lomeli over 3 years ago in reply to Alessandro Feriani

TI__Intellectual 1950 points

Yes, that's when i replied above with alarms getting completely cleared. I only got the alarms to trigger when i turned off the clock.

Understood, then please try 2EC instead.

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DAC3171 Alarm clocks