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ADC3683: Sampling clock (CLKP/M) differential levels (VID)

Claude Chevalier
Prodigy 30 points
Part Number: ADC3683
Other Parts Discussed in Thread: , CDCE62002, CDCM6208, SN65LVDS101, CDCLVP111-SP, LMX2615-SP, LMK04832-SP, SN65CML100, CDCLVP111, CDCE6214

Hi,

The ADC3683 datasheet specifies no minimum VID. Is there one? Will this work if driven from a standard LVDS driver (AC-coupled)?

Figure 8-12 makes it clear the higher the driving VOD, the better the performances.

Driving CLKP/M from a LVDS driver (eg FPGA IO) is not a good choice since typical LVDS VOD is 350mV (so, far left on the above graph).

What type of driver would you recommend to drive CLKP/M differentially and get a VID of > 1.5V? Can you provide a reference design?

Thanks!

  • 0
    TI__Mastermind 20865 points

    Hi Claude, one of our experts will respond to you shortly. Thanks

  • 0 in reply to Chase W
    TI__Genius 14281 points

    Hi Claude,

    The ADC3683EVM uses the CDC6214, which uses a LVDS driver and could be one option. If you are looking for a higher Vid than the CDC6214, you can look into using the CDCE62002 and CDCM6208. Both these use LVPECL and have a Vid closer to 1.5 Vpp range. 

    Regards, Amy

  • 0 in reply to Amy
    Prodigy 30 points

    Hi Amy,

    The ADC3683 will soon be available in the SEP (Space Enhanced Plastic) grade and we are looking at it for space use. I don't think the CDCxxx are valid options for space.

    But if I understand well, you are saying I could drive the ADC clokc from some LVPECL driver. So, what about SN65LVDS101 (LVDS-to-LVPECL)?

    Regards,

  • 0 in reply to Claude Chevalier
    TI__Genius 14281 points

    Hi Claude,

    I am checking with our clocking team for a possible space grade clocking solution. Will keep you posted!

    Regards, Amy

  • 0 in reply to Amy
    TI__Mastermind 30970 points

    Hi Claude,

    We have a few space grade devices. For just an LVPECL clock buffer, the CDCLVP111-SP is available and relatively inexpensive; it should be able to connect to an LVDS driver if AC-coupled. There are a handful of other PLL parts as well (LMK04832-SP and LMX2615-SP) which are significantly more expensive, but which support generating their own clock frequencies. For space-enhanced plastic options, if you're interested, please let me know - we don't have this at this time, but we're evaluating opportunities.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 30 points

    Hello Derek,

    To be honest, the CDCLVP111-SP  would be the most expansive part of our design. And to answer your question, I'm indeed looking for SEP parts.

    I think I could go CML rather than LVPECL. Do you have something similar to the SN65CML100 that has some space capabilities? Or some flight heritage (even though not formally a space part)?

    Regards,

    Claude

  • 0 in reply to Claude Chevalier
    TI__Mastermind 30970 points

    Claude,

    I don't think we have anything like SN65CML100 at this time. There was no SEP version of CDCLVP111 ever produced, and in general we're still a bit light on SEP parts in the clock buffers and interfacing space.

    If your timeline can accommodate a sampling device in mid August and a released device sometime around end of year, I might have an SEP option for you. If you've got a field apps contact and an NDA in place, we'd be able to share some preliminary information with you now (go through them directly, request a CTS contact and reference this thread); otherwise I can't say more on E2E, and the best I can do is check back in mid-August.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 30 points

    Derek,
    Is the "field app" you're talking of a TI employee or someone working for some official distributor (a FAE from Arrow)? I don't have any contact yet outside this forum.
    What is a CTS?

    Regards,

  • 0 in reply to Claude Chevalier
    TI__Mastermind 20865 points

    Hi Claude,

    So the field apps contact Derek is referring to is a TI employee with the title field applications engineer. They help interface between the product line applications/systems engineers at TI and our customers. CTS is referring to our Clocks and Timing Solutions team.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 30 points

    Hello,

    Two things. First, NDA is on its way.

    Second, when driven differentially, the CLKP/M pins must be AC-coupled as shown in figure 8-14 of the datasheet.

    Most clock drivers have a positive common-mode output voltage. For example, LVDS is ~1.2V, with a minimum output differential voltage of 250mV. At power-up, there will be a transient caused by the AC coupling capacitors and the internal 5k resistors. The response to the generic LVDS signal will look like this:

    At T0 (left of the above graph), the voltages on the CLKP/M pins are slightly exceeding the absolute max rating of the ADC (which is 2.1V).

    If I drive the CLKP/M pins with something exhibiting a larger differential swing (ti improve SNR as described inthe very top post above), voltages will go far above the absolute max.

    This transient doesn't last long. For instance, 0.1uF and 5k will require 1.5ms to reach steady-state.

    Is this an issue? Even the eval board with the CDCE6214 is exhibiting the same. Are there any guidelines about how high and for how long we can exceed the 2.1V absolute max?

    Thanks,

  • 0 in reply to Claude Chevalier
    TI__Mastermind 20865 points

    Hi Claude,

    I would not expect this to be an issue for the ADC, however I will check with the expert. Stay tuned!

    Regards, Chase

  • 0 in reply to Chase W
    TI__Genius 14281 points

    Hi Claude,

    What you describe above should not be an issue.

    Regards, Amy