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DAC121S101-Q1: tSUCL timing ?

Lee, Sam
Expert 5215 points
Part Number: DAC121S101-Q1

Hello team,

 

The tSUCL specifies min. 0ns (Tmin < TA < Tmax) in the DAC121S101-Q1 datasheet. However, the following waveform is measured with -10.6ns. It is not okay?

Currently, it’s difficult to meet the spec from Master side. tSUCL should be necessarily met? Any idea to solve this?

 

Thanks,

Sam Lee

  • 0
    TI__Mastermind 28648 points

    Hi Sam,

    Are you able to communicate with the device? This may run into trouble, but I can't say for sure. It's possible that the device could miss the communication is this spec is not met over temperature.

    It looks like you are using the same clock to generate /SYNC and SCLK, with the period for /SCLK doubled. Because of that, the falling edge of /SYNC starts at the same time as the rising edge of SCLK. Instead, is it possible to try making the width of /SYNC the same as the width of one of these SCLKs? That way, they have extra time for the SCLK rising edge.

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    TI__Expert 5215 points

    Hi Katlynne,

    Thank you for your reply.

    Unfortunaely, it's not possible to make /SYNC the same as the width of SCLK. Could you please check one more if it's acceptable from the IC design point of view? Or any other solution?

    Thanks,

    Sam Lee

  • +1 in reply to Lee, Sam
    TI__Mastermind 28648 points

    Hi Sam,

    I spoke with my team about this timing diagram. We typically don't require that there be a low to high transition on SCLK before the first falling edge of SCLK because SCLK is allowed to idle high or low. In this case, there would only be a requirement that the SYNC fall before the first SCLK falling edge. Your timing should be ok. 

    Best,

    Katlynne Jones