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ADS8588S: No Data on DOUTA pin.

Bharat Khanna
Prodigy 20 points
Part Number: ADS8588S

DOUTA pin only show output value of "0" when reading using SPI protocol.

The configuration of pins are as shown in the attached file.

 Steps followed.

              1) Setup Serial configuration as shown in the image.

              2) Provide 2 Analog(Sine wave) Mon_PD & BIASS_SENSE signal with frequency(500KHz) and Amplitude(peek to peek): 3.3 V.

              3) Read DOUTA(PIN 22) with SPI(SCLK = 500KHz).

 

Observation

1) CS verified, goes low during operation.

2) Clock verified on Pin 12 using oscilloscope.

3) DOUTA goes low during whole operation. Does not matter if analog input is connected or not.

 

Can you please tell what is missing/wrong?

Can you also please tell,

              How much is sampling frequency?

              What is recommended frequency of SPI-SCKL(Pin 12)?

  • 0
    TI__Mastermind 39545 points

    Hi ,

    Did you send a high pulse (>50ns) to the RESET pin to reset the ADC after the ADC is powered up?

    Your schematic looks good only except two minor issues:

    • The REFCAPA and REFCAPB should be shorted together and then decoupled to the AGND using a 10-uF capacitor, your are using two 10-uF capacitors, so only either C230 or 231 should be used.
    • The resistance on the AIN_xGND should match the resistance on the AIN_xP pin to minimize the offset error, you are using 1kohm resistor on the AIN_xGND pins and 100ohm resistor on the AIN_xP pins.

    A DC analog signal can be used to check if the conversion code is correct as a test purpose.

    The answers to your last two questions:

    • Your sampling rate is determined by your CONVSTA/B signal, which is 1/tcyc in the figure 1.
    • Your SCLK frequency is too slow so that you will not be able to retrieve the conversion data for all channels. Please check the details in the section 8.4.2.3.3 in the ADS8588S data sheet. The maximum SCLK frequency for the ADS8588S is 20MHz.

    Regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 20 points

    Hi Dale,

    Thank you for taking care of my issue and sharing information.

    Issue is solved by increasing SCLK frequency and following the timing as shown below.

    Previously CONVSTA/CONVSTB signal were not controlled.

    Regards

    Bharat

  • 0 in reply to Bharat Khanna
    TI__Mastermind 39545 points

    Hi Bharat,

    Thank you for your update.

    Regards,

    Dale