ADS1261: -

Dominik Schlachter

Part Number: ADS1261
Other Parts Discussed in Thread: ADS124S08

I hope you can support us on following issue:

the ADC is to sample synchronized to an analog signal from the microcontroller. The synchronization is solved by a shared clock between ADC and microcontroller. For this purpose it is important to know the timing of the ADC exactly in order to synchronize the signals. During this task several problems or questions came up, which we would like to clarify.

Questions about the behavior of the ADC:

- Is it basically allowed to use other frequencies - Basically the datasheet gives a range in which the ADC can be operated. However, other data sheet passages explicitly refer to 10.24 MHz or 7.3728 MHz (chapter 9.4.4).

-Is the calibration capability given for frequencies not equal to 10.24 MHz or 7.3728 MHz (see data sheet chapter 7.3)? How long does the calibration take for deviating frequencies?

- The application note linked to the ADS1261 gives many hints about the conversion latency, but not much is said about the calibration time. Currently, our measurements of the calibration time do not provide reproducible results. This results in inconsistent results when recording the calibration time.

- How does the conversion latency depend on the input frequency? Is there an exact breakdown?

- The application note states that the sampling time basically consists of a programmable delay, the actual sampling time and an overhead. On the one hand, the question is whether a delay of 50 uS also scales with the clock frequency, and on the other hand, how the overhead is composed (for example, there is information for the ADS124s08 in the application note as a table, something like that would be very helpful)

- The datasheet talks about a 4th order Delta Sigma modulator, one question is what exactly the 2+2 pipelining means for the application (or the question: Is this relevant for our application?).

- What is the exact calculation basis of the sampling rate depending on the clock? Does the calculation basis work for the whole range, i.e. also for very low frequencies? For example, if a clock of 1 MHz is set at 40 kSPS I had to split the answer, because of the limitation in text field.

If you have any technical questions, please contact Mr. Will-Groo directly (paul.will-groo@ifm.com).

Best regards Dominik Schlachter

over 3 years ago

0 Bryan Lizon86 over 3 years ago

TI__Guru 52586 points

Hi Dominik,

I believe your questions are answered below. Many of these can be resolved by reading through the conversion latency app note (https://www.ti.com/lit/sbaa535) in detail, specifically sections 5.5 and 8.8

Dominik Schlachter said:
-Is the calibration capability given for frequencies not equal to 10.24 MHz or 7.3728 MHz (see data sheet chapter 7.3)? How long does the calibration take for deviating frequencies?

The calibration time is given in Table 14 in the ADS1261 datasheet. Note this is for the nominal clock frequency. If you are using a different clock frequency, the times would scale. This is described in the app note. Specifically, section 5.5 in that app note discusses how conversion latency changes with changing clock frequency. Additionally, section 8.8 steps through an example using the ADS1261 where a 4 MHz clock is used (but the same principles apply to any valid clock frequency)

Dominik Schlachter said:
How does the conversion latency depend on the input frequency? Is there an exact breakdown?

The conversion latency does not really depend on the input signal frequency. Conversion latency in low-speed delta-sigma ADCs is almost entirely related to the digital filter setting, as described in the aforementioned app note

Dominik Schlachter said:
The application note states that the sampling time basically consists of a programmable delay, the actual sampling time and an overhead. On the one hand, the question is whether a delay of 50 uS also scales with the clock frequency, and on the other hand, how the overhead is composed (for example, there is information for the ADS124s08 in the application note as a table, something like that would be very helpful)

This question is answered in section 5.5 of the app note (Clock Frequency). An example is shown in Section 8.8. I do not have a table of values readily available for the ADS1261 like we do for the ADS124S08, but you can back-calculate the overhead time for the ADS1261 using the methods described in the app note. I am not sure this is really necessary for what you are trying to accomplish however

Dominik Schlachter said:
The datasheet talks about a 4th order Delta Sigma modulator, one question is what exactly the 2+2 pipelining means for the application (or the question: Is this relevant for our application?)

This should not be relevant for your application, this is merely how the modulator is designed. The most important questions for you to answer are whether the ADC noise performance and conversion latency are sufficient for your application (the latter of which is discussed in this e2e post and the app note

Dominik Schlachter said:
What is the exact calculation basis of the sampling rate depending on the clock? Does the calculation basis work for the whole range, i.e. also for very low frequencies? For example, if a clock of 1 MHz is set at 40 kSPS I had to split the answer, because of the limitation in text field.

It seems like this question might have gotten cut off, but again, the answer is in section 5.5 of the app note. Basically, the oversampling ratio is always the same, so if you use a lower clock frequency compared to the nominal, the output data rates will scale accordingly.

I would strongly encourage you to check out Section 8.8 in the app note for an example of how the ADS1261 parameters scale when the clock frequency changes.

-Bryan

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ADS1261: -