In the case of EEG measurement, noise of 50Hz/60Hz from commercial power supply is superimposing on the electrode cable.
Is there any way to reduce the noise?
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1. May I ask what was the power source used to supply power to the ADS1299? Is it properly grounded and shielded? Does it have some inlet filter or ferrite bead(chips)?
Does customer find 50Hz/60Hz noise else where on other parts of PCBAs?
Suggestions and Comments are to first make sure the power source are clean e.g. ADS1299 EVM user guide suggest to use battery power to see if it improves/helps.
2. And, may I ask what was the signal source? Was the signal source clean/free of 50Hz/60Hz noises?
Can customer do some external and/or internal short tests to see whether the 50Hz/60Hz noises still exist/appear and/or the magnitude difference?
3. Does it use a clean linear voltage regulator? Does the customer try to follow the ADS1299 evaluation kit/boar(EVM)' s design?
E.g. in the ADS1299EVM user guide page 51, there are many low pass filters with differential capacitors.
4. Does customer use the BIASOUT feature for common mode noise suppression.
You have a basic misunderstanding. The issue is different from the power supply to ADS1299. 50Hz and 60Hz noise come from AC100V power-line and the cable of EEG device picks up 50Hz/60Hz. We can not ignore this noise to measure EEG signal. Therefor ADS1299 should have a digital filter to suppress such noise more than 40dB. I'd like to know ADS has such function. If it is difficult, please let me know the other measures.
According to ADS1299 datasheet
Page 25~26 Section 184.108.40.206 Digital Decimation Filter
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in EEG applications for ac lead-off detection.
The digital filter on each channel consists of a third-order sinc filter. The sinc filter decimation ratio can be
adjusted by the DR bits in the CONFIG1 register (see the Register Maps section for details). This setting is a
global setting that affects all channels and, therefore, all channels operate at the same data rate in a device.
The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these
frequencies, the filter has infinite attenuation.
Customer may want to try different data rate(CONFIG register DR[2:0] bits) to see if it improves.
In addition to that, Page 66~69 Section 10.2.2 Detailed Design Procedure suggests the following -
The passive components RFilt and CFilt form low-pass filters. In general, the filter is advised to be formed by using
a differential capacitor CFIlt that shunts the inputs rather than individual RC filters whose capacitors shunt to
ground. The differential capacitor configuration significantly improves common-mode rejection because this
approach removes dependence on component mismatch.
The cutoff frequency for the filter can be placed well past the data rate of the ADC because of the delta-sigma
ADC filter-then-decimate topology. Take care to prevent aliasing around the first repetition of the digital
decimation filter response at fMOD. Assuming a 2.048-MHz fCLK, fMOD = 1.024 MHz. The value of RFilt has a
minimum set by technical standards for medical electronics. The capacitor value must be set to arrange the
proper cutoff frequency.
The integrated bias amplifier serves two purposes in an EEG data acquisition system with the ADS1299. The
bias amplifier provides a bias voltage that, when applied to the patient, keeps the measurement electrode
common-mode voltage within the rails of the ADS1299. This scenario allows for dc coupling. In addition, the bias
amplifier can be configured to provide negative common-mode feedback to the patient to cancel unwanted
common-mode signals appearing on the electrodes. This feature is especially helpful because biopotential
acquisition systems are notoriously prone to mains-frequency common-mode interference.
If the measurement setup was a single-ended configuration without shielding, the measurement setup was subject to
significant mains interference. A digital low-pass filter needs to be applied to remove the interference.
So, customer may consider designing digital filter to suppress/notch the 50/60 Hz Main.
Thank you for the advise.
May I understand your conclusion is that I should use the sinc filter has notches (or zeroes) ?
Indeed the sinc filter has such function and I can see it in figure 27 Sinc Filter Frequency Response.
1) As a background the input noise must be lower than 3uVpp, therefor Data Rate is 250 or 500 or 1000 from Table 2.
2) When fIN/FDR =1(DR=250SPS), the notch frequency becomes 250Hz. The reduction 0f 50Hz/60Hz is only -10 dB from figure 27. Also the cut-off frequency must be larger than 40Hz for EEG use.
Please tell me the register setting the notch frequency to 50Hz or 60Hz
Digital filter is integrated and automatically applied in in the device. Customer can adjust the filter's different frequency responses(shown in datasheet page 26) based on the CONFIG1 register DR[2:0] bits settings; this is something customer may want to test, collect data, study, analyze, verify and validate, and tune -
In addition to that, Page 66~69 Section 10.2.2 Detailed Design Procedure suggests use passive components RFilt and CFilt form low-pass filters. In general, the filter is advised to be formed by using a differential capacitor CFIlt that shunts the inputs rather than individual RC filters whose capacitors shunt to
ground. The differential capacitor configuration significantly improves common-mode rejection because this approach removes dependence on component mismatch.
How is the customer's shielding? If the product is not powered by batteries, Customer may want to improve their shielding method or technique to reduce/suppress the 50/60 MAIN interference.
So, customer may also need to consider designing their own digital filter to suppress/notch the 50/60 Hz Main interference.
Thank you for the advise.
However the answers is always not easy to understand. I would be happy if you and the other members would reply logically.
Anyway I understand that I need another digital filter besides ADS1299 to reduce 50Hz/60Hz noise. Is it correct?
Also please show me the schematic of the differential capacitor configuration.
Our EEG sensor works by battery, however sensor cables pick up commercial 50Hz/60Hz power noise.
If the suggested solution still not works well to solve the MAIN interference, yes, customer may need another digital filter to reduce 50/60 Hz noise.
Also, does customer use the BIAS Amplifier and BIASOUT? It's one of the methods to suppress the common mode noises.
The suggested schematic of the differential capacitor configuration is described in the datasheet Page 66~69 Section 10.2.2 Detailed Design Procedure mentioned above with screenshot.
The ADS1299 EVM user guide page 51 also has/shows reference designs for the differential capacitors.
Please check and make sure sensor cables also have good shielding.