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LM98722: ADC output variates depending on number of white pixels

Part Number: LM98722

I have an interesting issue.

I use the AFE as a front end to a 3 channel CIS head. I am running in Sample/Hold mode, and master mode and SH_R is unconnected. Coarse and fine turning of the Pixel phase is done, to uptimize the position of the clamping.

Now when I scan a white sheet of paper I get something strange.

Lets say I scan at the left (channel 1). The paper covers the full channel, and a bit of channel 2.

The median value of the white pixels in channel 1 is around 120.

The few pixels that are white in channel 2 have a median value of 200.

Now if I make a second scan where I place the white paper at channel 2, the "white" pixels have a median value of 120, while the few pixels in channel 1 and 3 are 200.

If I place the paper half/half the median value is around 160.

I have measured the input to the AFE, and it is stable.. it does not change its level depending on the number of pixels that are convered.

Is this issue known and help to point me in the right direction is highly appriciated Slight smile

  • Hello Henrik,

    Thank you for your interest in the LM98722. I will forward the question to the appropriate expert. Please expect a response by July 8th.

    Could you provide additional details about your setup?

    • In section 7.4 Device Functional Modes
      • It seems you are utilizing Mode 3 - Three Channel Input/Synchronous Pixel Sampling. Is this correct?
    • Section 7.4.12 reference an Automatic Black and White Level Calibration Loops. Are you utilizing these feedback/calibration loops to adjust offset & gain for the ADC outputs?

    Best regards,

    Bill Chieng

  • Hi Bill.

    Yes I am using mode 3. I supply a pixel clock of 8Mhz. And no I am not using the automatic black/white level calibration, as the AFE is driven in master mode, and is not getting the Frame Sync signal. It does not know when a CIS lines starts.

    I have tried two different configurations (ADDriverTransmitAndVerify takes 3 arguments (address, value, bitmask to compare when read back)

    CONFIG 1:

    ADDriverTransmitAndVerify( 31, 0x0U, 0xFFU ); /* page 0 */

    ADDriverWait( 0, 0x80 );

    ADDriverTransmitAndVerify( 0, 0x00U, 0x1U ); /* unlock */

    ADDriverTransmitAndVerify( 31, 0x8U, 0xFFU ); /* page 8 */
    ADDriverTransmitAndVerify( 4, 0x04U, 0xFFU ); /* Cmos */

    ADDriverTransmitAndVerify( 31, 0x0U, 0xFFU ); /* page 0 */
    ADDriverTransmitAndVerify( 0, 0x22U, 0x7FU ); /* start */
    ADDriverTransmitAndVerify( 1, 0x40U, 0xFFU ); /* Power up */
    ADDriverTransmitAndVerify( 2, 0xC4U, 0xFFU ); /* pixel clock, SH mode */
    ADDriverTransmitAndVerify( 3, 0x80U, 0xFFU ); /* white scan results in rising voltage */
    ADDriverTransmitAndVerify( 4, 0x10U, 0xFFU ); /* VCLP disabled, external voltage supplied */
    ADDriverTransmitAndVerify( 5, 0xE0U, 0xFFU ); /* Cmos */

    /* registers 8 - 19 ( start stop clock for 3 clamp and start stop for 3 sample lines ) */
    for( uint16_t u16Index = 8U; u16Index < 20U; u16Index += 2U )
    {
    const uint8_t u8StartClock = 22U;
    const uint8_t u8StopClock = 38U;
    ADDriverTransmitAndVerify( ( uint8_t ) u16Index, u8StartClock, 0xFFU ); /* Clamp */
    ADDriverTransmitAndVerify( ( uint8_t ) u16Index + 1U, u8StopClock, 0xFFU ); /* Sample */
    }

    ADDriverTransmitAndVerify( 0, 0x23U, 0x7FU ); /* Lock and start */

    CONFIG 2:

    ADDriverTransmitAndVerify( 31, 0x0U, 0xFFU ); /* page 0 */

    ADDriverWait( 0, 0x80 );

    ADDriverTransmitAndVerify( 0, 0x00U, 0x1U ); /* unlock */

    ADDriverTransmitAndVerify( 31, 0x8U, 0xFFU ); /* page 8 */
    ADDriverTransmitAndVerify( 4, 0x04U, 0xFFU ); /* Cmos */

    ADDriverTransmitAndVerify( 31, 0x1U, 0xFFU ); /* page 1 */
    ADDriverTransmitAndVerify( 0, 0, 0xFFU ); /* 1x gain */


    ADDriverTransmitAndVerify( 31, 0x0U, 0xFFU ); /* page 0 */
    ADDriverTransmitAndVerify( 0, 0x02U, 0x7FU ); /* start */
    ADDriverTransmitAndVerify( 1, 0x42U, 0xFFU ); /* Power up */
    ADDriverTransmitAndVerify( 2, 0xC4U, 0xFFU ); /* pixel clock, SH mode */
    ADDriverTransmitAndVerify( 3, 0x00U, 0xFFU ); /* white scan results in rising voltage */
    ADDriverTransmitAndVerify( 4, 0x08U, 0xFFU ); /* VCLP disabled, external voltage supplied */
    ADDriverTransmitAndVerify( 5, 0xE0U, 0xFFU ); /* Cmos */

    /* registers 8 - 19 ( start stop clock for 3 clamp and start stop for 3 sample lines ) */
    for( uint8_t u8Index = 8U; u8Index < 20U; u8Index += 2U )
    {
    const uint8_t u8StartClock = 33U;
    const uint8_t u8StopClock = 37U;
    ADDriverTransmitAndVerify( u8Index, u8StartClock, 0xFFU ); /* start */
    ADDriverTransmitAndVerify( u8Index + 1U, u8StopClock, 0xFFU ); /* stop */
    }

    ADDriverTransmitAndVerify( 0, 0x23U, 0x7FU ); /* Lock and start */

    Config 1 is better than config 2, but not perfect, scanning still variates too much.

  • Ah.. found the culprit.. the AFE had wrong components in the signal line.... Thanks for the quick response anyway :)