This is in connection with thread ADS5407: How to read negative values from high speed ADCs - Data converters forum - Data converters - TI E2E support forums
Clock issues are raised seperately
1. Do i really require a jitter cleaner as used for JESD ADCs ? Are they required for Sub-GHz ADCs if so ? kindly suggest one
2. What is the ideal mechanism of clock control, is it better if i generate the clock on my ADC board and give it to FMC ?
or should i take CLK from FMC and give to ADC ?
any way the programmer on FPGA side would sample the data based on his input recieved over DATCLK pins of ADS5407
which will be better option CLK Driven from FMC or CLK Generated Locally
Kindly suggest a TI Clock source for Input to ADC ADS5407