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Need for Jitter Cleaner and choosing the position of the clock source

Other Parts Discussed in Thread: ADS5407

This is in connection with thread ADS5407: How to read negative values from high speed ADCs - Data converters forum - Data converters - TI E2E support forums

Clock issues are raised seperately

1. Do i really require a jitter cleaner as used for JESD ADCs ? Are they required for Sub-GHz ADCs if so ? kindly suggest one

2. What is the ideal mechanism of clock control, is it better if i generate the clock on my ADC board and give it to FMC ?

or should i take CLK from FMC and give to ADC ?

any way the programmer on FPGA side would sample the data based on his input recieved over DATCLK pins of ADS5407

which will be better option CLK Driven from FMC or CLK Generated Locally

Kindly suggest a TI Clock source for Input to ADC ADS5407

  • Hi Shyam,

    I am sending this over to the clock team for a recommendation.



  • Hi Shyam,

    1. No, jitter cleaner is needed when there is a noisy reference and wants to have cleaned output. Regarding the JESD ADC clock requirement, you would need an JESD clock gen, which can can produce device clock along with SYSREF out. Clocking device can be used in jitter cleaner mode or normal clock gen mode based on requirement. 

    For non-jesd ADC, you doesn't needed JESD clocks out but based on reference in and jitter requirement, you can choose jitter cleaner.

    2. Usually it should be good clocks at ADC card, as it may get the programming control from FPGA through FMC and FPGA can get the DATCLK from ADC.



    Ajeet Pal