ADC34J44EVM: Configuring LMK04828 to use CLK1IN on J10 as the clock source

Currently : PLL2 is locked :PLL1 is NOT clocked. CLK1 is 100MHz supplied from an external quality oscillator. I can see from setting the status LEDS that CLK1 is selected, and that LOS is not asserted.

I have screen grabs from the ADC3000 GUI and the  .cfg file that I am working on. I would upload these, but it doesn't seem to let me.

In my project, sometimes it will be necessary to sync two separate systems from the same external clock source. Most of the time, however,  systems will be separate and use their own oscillator. So it is important that I can get all the functionality working. 

Hi Steve,

I am checking into this and will get back to you soon.

Regards, Amy

Hi Steve,

I have the board setup in lab and will give you an update tomorrow.

Regards, Amy

Hi Steve, in the meantime, could you send us the ADC config files that you are using? I would suggest setting the CLKin1 R divider and the N divider on the PLL1 tab to the same value (for example: 150 for both). This will allow only a single register change to switch from using the external oscillator through J10 to using the onboard 100MHz VCXO and visa-versa. All that should be necessary is to tri-state the PLL1 charge pump, then the onboard VCXO is used to lock PLL2.

Thanks, Chase

Hi Steve, something else that just came to mind is that you may need to synchronize the LMK04828 dividers across all of the evm boards in your test system. Typically the difference is negligible however it can be something to look into when the time comes to synchronize the ADCs. We can help out with the LMK divider alignment process if needed, just let us know!

Thanks, Chase

Hi Chase,

This issue is still not resolved (I've been off work). I'm back on it now.

I have an external 100MHz for clkin1. R=N=150. Using the status outputs I can see 667KHz at "R" & "N". I can see Clkiin1 is selected and LOS is not asserted. CPout1 always seems to be 2.75V, it does seem to try to tweak the oscillator.  I've tried changing the "Charge Pump Polarity" , enabling/disabling the charge pump and tweaking R/N to unstable values and the CPout1 voltage does not change. The control range for the oscillator is 0 to 3.3V. Do I need to change any of the associated components R40/C77/C76/R94? Also do you have a working config file you can send me to try?

I sent you my config as a reply to your email, but now I've seen it has "no reply" in the title.

Your website won't allow me to upload the .cfg file, so I will add the text below

CLKIN1_PLL1_not_locking_250722.cfg...

LMK04828
0x00 0x00
0x02 0x00
0x100 0x00
0x101 0x55
0x103 0x00
0x104 0x20
0x105 0x00
0x106 0x30
0x107 0x76
0x108 0x10
0x109 0x55
0x10B 0x00
0x10C 0x20
0x10D 0x00
0x10E 0x70
0x10F 0x11
0x110 0x08
0x111 0x55
0x113 0x00
0x114 0x00
0x115 0x00
0x116 0x79
0x117 0x01
0x118 0x08
0x119 0x55
0x11B 0x00
0x11C 0x00
0x11D 0x00
0x11E 0x79
0x11F 0x01
0x120 0x10
0x121 0x55
0x123 0x00
0x124 0x00
0x125 0x00
0x126 0x79
0x127 0x01
0x128 0x08
0x129 0x55
0x12B 0x00
0x12C 0x00
0x12D 0x00
0x12E 0x79
0x12F 0x01
0x130 0x02
0x131 0x55
0x133 0x00
0x134 0x00
0x135 0x00
0x136 0x79
0x137 0x00
0x138 0x04
0x139 0x03
0x13A 0x01
0x13B 0x40
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x06
0x140 0x03
0x141 0x00
0x142 0x00
0x143 0x13
0x144 0xFF
0x145 0x00
0x146 0x10
0x147 0x1A
0x148 0x02
0x149 0x43
0x14A 0x02
0x14B 0x16
0x14C 0x00
0x14D 0x00
0x14E 0x00
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
0x153 0x00
0x154 0x96
0x155 0x00
0x156 0x96
0x157 0x00
0x158 0x96
0x159 0x00
0x15A 0x96
0x15B 0x07
0x15C 0x20
0x15D 0x00
0x15E 0x00
0x15F 0x0B
0x160 0x00
0x161 0x0A
0x162 0x04
0x163 0x00
0x164 0x00
0x165 0x0C
0x166 0x00
0x167 0x00
0x168 0x20
0x169 0x59
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
0x17C 0x15
0x17D 0x0F
ADC34Jxx
0x00 0x00
0x01 0x00
0x02 0x00
0x03 0x00
0x04 0x00
0x05 0x00
0x06 0x00
0x09 0x00
0x0A 0x00
0x0B 0x00
0x0C 0x00
0x0D 0x00
0x0E 0x00
0x0F 0x00
0x13 0x00
0x15 0x00
0x17 0x00
0x27 0x00
0x2A 0x00
0x2B 0x00
0x2F 0x00
0x30 0x00
0x31 0x00
0x34 0x00
0x3A 0x00
0x3B 0x00
0x3C 0x00
0x70A 0x00

Hi Steve,

We don't have a configuration created for this just yet, however Amy will work on this for you. I have taken a quick glance and see that the configuration you provided shows the ADC clock as 160MHz and the FPGA reference clock as 80MHz. Can you verify these are correct so Amy can create the configuration file for you? Also, you shouldn't have to make any modifications to the components that you listed.

Something to try, can you enable the CLKout6 output (on the Clock Outputs tab) and set the divider to be 10 and then measure the output at J13 with an oscilloscope? The expected output would be 256MHz.

Regards, Chase

Hi Chase,

I hadn't setup the output clocks on that particular config file, as I was focused on getting PLL1 to clock. PLL2 was locking, so I was happy with that.

I've updated the whole config file, so it reflects my overall design, with most output clocks being 100MHz. This is included as text at the end.

My overall test for correct implementation is to use a scope, one channel on "clkin1" and the other on Y1_PIN4. I repeat trigger on clkin1 with a hold off off 230ms. I see Y1_PIN4 wander around wrt "clkin1".

Eval_CLKIN1_PLL1_not_locking_260722.cfg

LMK04828
0x00 0x00
0x02 0x00
0x100 0x1A
0x101 0x55
0x103 0x00
0x104 0x20
0x105 0x00
0x106 0x30
0x107 0x76
0x108 0x1A
0x109 0x55
0x10B 0x00
0x10C 0x20
0x10D 0x00
0x10E 0x70
0x10F 0x11
0x110 0x0D
0x111 0x55
0x113 0x00
0x114 0x20
0x115 0x00
0x116 0x71
0x117 0x01
0x118 0x1A
0x119 0x55
0x11B 0x00
0x11C 0x20
0x11D 0x00
0x11E 0x71
0x11F 0x01
0x120 0x1A
0x121 0x55
0x123 0x00
0x124 0x20
0x125 0x00
0x126 0x71
0x127 0x11
0x128 0x1A
0x129 0x55
0x12B 0x00
0x12C 0x20
0x12D 0x00
0x12E 0x71
0x12F 0x01
0x130 0x1A
0x131 0x55
0x133 0x00
0x134 0x20
0x135 0x00
0x136 0x71
0x137 0x01
0x138 0x04
0x139 0x02
0x13A 0x01
0x13B 0x40
0x13C 0x00
0x13D 0x08
0x13E 0x03
0x13F 0x00
0x140 0x01
0x141 0x00
0x142 0x00
0x143 0x13
0x144 0xFF
0x145 0x00
0x146 0x10
0x147 0x1A
0x148 0x02
0x149 0x4B
0x14A 0x02
0x14B 0x16
0x14C 0x00
0x14D 0x00
0x14E 0x00
0x14F 0x7F
0x150 0x03
0x151 0x02
0x152 0x00
0x153 0x00
0x154 0x96
0x155 0x00
0x156 0x96
0x157 0x00
0x158 0x96
0x159 0x00
0x15A 0x96
0x15B 0x00
0x15C 0x00
0x15D 0x00
0x15E 0x00
0x15F 0x0B
0x160 0x00
0x161 0x0E
0x162 0xE5
0x163 0x00
0x164 0x00
0x165 0x0C
0x166 0x00
0x167 0x00
0x168 0x1A
0x169 0x59
0x16A 0x20
0x16B 0x00
0x16C 0x00
0x16D 0x00
0x16E 0x13
0x17C 0x15
0x17D 0x0F
ADC34Jxx
0x00 0x00
0x01 0x00
0x02 0x00
0x03 0x00
0x04 0x00
0x05 0x00
0x06 0x00
0x09 0x00
0x0A 0x00
0x0B 0x00
0x0C 0x00
0x0D 0x00
0x0E 0x00
0x0F 0x00
0x13 0x00
0x15 0x00
0x17 0x00
0x27 0x00
0x2A 0x00
0x2B 0x00
0x2F 0x00
0x30 0x00
0x31 0x00
0x34 0x00
0x3A 0x00
0x3B 0x00
0x3C 0x00
0x70A 0x00

Hi Steve,

Thank you for providing your register writes. I am checking into this and will give you an update tomorrow. 

Regards, Amy

Hi Amy,

If you copy and paste the register writes into a text file and rename it "<file>.cfg" it will be a functioning config file. I could not easily upload my config file directly.

Regards

Steve

Hi Steve,

Thank you for your question. This board appears to have a default configuration that pulls the charge pump high. Try removing R40 near the LMK - this should resolve the issue and allow PLL1 to lock. 

Regards, Amy 

Hi Amy,

I removed R40, and PLL1 is still not locking. Y1 pin 1 is at 1.65V. This stays at this voltage even if I fiddle around with "Charge Pump Gain", "Charge Pump Polarity" , "Charge Pump Tri-state" or "N_divider".  Before removal of R40 (24.9ohms) Y1 pin 1 measured 2.75V, and this also did not respond to the above parameters. On the EVM schematic (sheet7) there is a note "R40 and C77 form a voltage divider" which would seem to imply that R40 is necessary. Would a different value help?

Does my config file lock PLL1 on your EVM system?

Do you have a working config file to send me from a system where PLL1 is locking to an external 100MHz clock ?

That would be a great help.

Best Regards

Steve Joures

Hi Amy,

In my application CPout1 will be tri-stated mainly, but sometimes used with an external clock. Would I need a high value pullup or pulldown on R40 to prevent the VCXO frequency wandering?

Regards

Steve Joures

Hi Amy,

After further tests it appears that Clkin1 R & N need be 30 or less for a reliable lock.

Regards

Steve Joures