DAC3283: DAC ,SPURIOUS ,SFDR,FDAC,sample rate,Bandwidth,Sampling frequency

BALAMURUGAN V

Part Number: DAC3283
Other Parts Discussed in Thread: CDCE62005,

I am doing a project using DAC 3283 using artix 7 FPGA and also using CDCE62005 the requird data clock and dac clock is generated and gave input to DAC3283.
DAC_CLK Sampling frequency is 400 msps . The digital input given to DAC3283 is 10MHz using DDS complier in xilinx vivado 18.2 tool. The analog output we got was
10 MHZ with 3.22 dbm which is observed by using spectrum analyser. but ckecking the spurious level by setting 1Kz restive bandwidth(RSW) and vedio bandwisth(VBW) around 10 hz with span range of
500KHZ , we got 57 dbc . In data sheet , showen that for 10mhz spurious level will be around 80dbc to 85dbc. Now for my generated 10Mhz needed spurious level which is greater than 75.
and how can i achieve it ?K

inldy reply with better solution.

Thanks in advance

over 2 years ago

0 Kang Hsia over 2 years ago

TI__Guru 70144 points

Hi Bal,

Please advise if you can capture the spectrum analyzer output. The DAC spur within 500kHz is primarily caused by external coupling from pollutions due to:

1. DC/DC switcher switching at 500kHz

2. other clocking components with 500kHz contributions.

3. quality of the clock noise. The CDCE62005 phase noise should have good noise floor at 500kHz offset with 400MHz clock.

The DAC output itself should not have any components at 500kHz offset. A spectrum plot will help.

0 Kang Hsia over 2 years ago

TI__Guru 70144 points

Hi Bal,

Please advise if you can capture the spectrum analyzer output. The DAC spur within 500kHz is primarily caused by external coupling from pollutions due to:

1. DC/DC switcher switching at 500kHz

2. other clocking components with 500kHz contributions.

3. quality of the clock noise. The CDCE62005 phase noise should have good noise floor at 500kHz offset with 400MHz clock.

The DAC output itself should not have any components at 500kHz offset. A spectrum plot will help.

0 BALAMURUGAN V over 2 years ago in reply to Kang Hsia

Prodigy 20 points

Hi Kang ,

thanks for your kindly reply.As i mentioned early the 500khz is not spurious ,the spurious level we get is mentioned dbc only..exactly 65 dbc.

How can I improve the spurious level from 65dbc to 85 dbc .

even we set the span ratio of 1MHz still we get the spurious level in 65dbc.

Is there any possible way to increase the spurious level better using DAC3283.?

0 Kang Hsia over 2 years ago in reply to BALAMURUGAN V

TI__Guru 70144 points

Hi Bal,

Please advise if you can take a spectrum analyzer plot. I do not see DAC3283 having a spur this much within 1MHz span.

If you are seeing 65dBc of "noise" then it is the phase noise of the clock source provided to the DAC. In this case, you will need to reach out to the clocking team to get advise on the quality of the clock.

You may see the following app note for detail

https://www.ti.com/lit/an/slaa566/slaa566.pdf?ts=1658151148868&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDAC3482%253Futm_source%253Dgoogle%2526utm_medium%253Dcpc%2526utm_campaign%253Dasc-null-null-GPN_EN-cpc-pf-google-wwe%2526utm_content%253DDAC3482%2526ds_k%253DDAC3482%2526DCM%253Dyes%2526gclid%253DCj0KCQjwidSWBhDdARIsAIoTVb06Fv8s2GUtp9XpTiSCCMbOmX5d97FGup-g8_o3cS_o1q02iGWmBr4aAvOgEALw_wcB%2526gclsrc%253Daw.ds

Even within very narrow bandwidth, the DAC's phase noise performance should be less than 65dBc

0 BALAMURUGAN V over 2 years ago in reply to Kang Hsia

Prodigy 20 points

Hi Kang ,

Even I checked with the phase noise of the clock source quality ,the same problem occurs. we have tried all the way given by the hardware team but the results are same ..spurious level still not better. Still searching for better solution to overcome this problem in both hardware and also in software part .

0 Kang Hsia over 2 years ago in reply to BALAMURUGAN V

TI__Guru 70144 points

Hi Bal,

Could you please advise the spectrum plot?

You will also need to post your question on the clocking forum for support as this is now a clock quality issue.

Thanks.

-Kang

0 BALAMURUGAN V over 2 years ago in reply to Kang Hsia

Prodigy 20 points

Hi kang,

I hereby attached the spectrum plot.I shows the Marker M1 as 10MHz output with -2.79dbm, and D2 is its corresponding spurious lvel of -60.25dB. Kindly concern.

0 BALAMURUGAN V over 2 years ago in reply to BALAMURUGAN V

Prodigy 20 points

+1 Kang Hsia over 2 years ago in reply to BALAMURUGAN V

TI__Guru 70144 points

Hi Bal,

This is a classic sign of a 20kHz oscillation is coupled onto the CDCE62055 or DAC3283 power supplies. Please check:

1. any 20kHz frequencies generation circuits or power supplies. Power supplies with DC/DC converters may have 20kHz offset.

2. we also know if one DC/DC converter is switching at 480kHz, and another one at 500kHz, there could be beat frequencies generated at 20kHz.

3. any clock sources at 20kHz

The DAC3283 itself does not have such spurs. We have checked on the EVM.

-Kang

0 BALAMURUGAN V over 2 years ago in reply to Kang Hsia

Prodigy 20 points

Hi Kang,

Thanks for kind reply .

Since we are using two types of DC/DC converters,one for DAC and CDCE and another one for OCXO oscillator .The both converters are having two different switching frequency and that is the problem as you mentioned in last thread.We just tested with separate on board crystal oscillator we get the spurious is 0dB. We must use OCXO so we need to match switching frequency of both regulators to solve the problems i think so..anyway great thanks for your guindance.

0 Kang Hsia over 2 years ago in reply to BALAMURUGAN V

TI__Guru 70144 points

Hi Bal,

Thank you for your update! good to hear.

-Kang

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DAC3283: DAC ,SPURIOUS ,SFDR,FDAC,sample rate,Bandwidth,Sampling frequency