The DAC7718 datasheet specifies that AVDD/AVSS should be applied after DVDD/IOVDD. I'd like to know a bit more about the internal rail architecture, why this restriction exists, and what the consequences of violating this power-on restriction might be (would it cause damage to the device, or just undefined behavior?).
My design currently has certain states where AVDD/AVSS may be powered, with DVDD/IOVDD unpowered for extended periods of time. I can place load switches on the AVDD/AVSS rails to sequence them properly, but would prefer not to if it can be avoided.
