• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 46 subscribers
  • Views 2013 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC7718, no offset output

Mark81
Expert 2610 points
Other Parts Discussed in Thread: DAC8718, DAC7718EVM

Hello,

 

I have a board with a DAC7718, used in bipolar mode (±12V). Other settings: WAKEUP, RST, LDAC, RSTSEL and USB/BTC are pulled-up. Vref is 2,5V, gain is set to 4x, no correction engine.

I can successfully communicate with the device (write-only, I don't have SDO routed) and I can update the DAC output.

 

The problem is the voltage range is between 0 and 10V, instead of -5 and 5V. In fact, the offset outputs voltage is 0V instead of 1.67V as stated in the datasheet (table 6, pag. 39).

Writing to the offset registers changes nothing, that is the offset output voltages are always 0V.

 

Did anyone run into this issue?

Thanks

Marco

  • 0
    TI__Mastermind 43915 points

    Hi Marco,

    What is the power supply sequence that you are using? Are you following the power on reset power supply sequencing order that is described in the DAC8718 datasheet? If is important that Vref comes up last following the other supplies. Also, if you post a schematic of your setup, we can make sure that you have all the static I/O lines properly set.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Expert 2610 points

    Hi Tony,

    my schematic is very similar to the DAC7718EVM, but the RC network on the Vref. I bet it provides the required delay to Vref. I'll try to add that network to my board, if it doesn't fix the issue I'll post the schematic.

    Thank you
    Marco

     

  • 0 in reply to Mark81
    TI__Mastermind 43915 points

    Marco,

    It is also important that the DVDD and IOVDD come up before the high voltage supplies. We also list the state of some of the static I/O lines we recommend being pulled up/down through weak pull up resistors at power up.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Expert 2610 points

    Tony,

    how to achieve the correct sequencing? It seems quite difficult to apply all power sources one-by-one. The schematic of the development board:

    http://www.ti.com/lit/ug/sbau165a/sbau165a.pdf

    shows just the RC delay for REFx, but the others seems to be applied at the same time.
    Anyway, this is my current design (I've already inserter the RC network con Vref).

    I still have a unipolar output.

     

    EDIT: image not visible with the editor command. I uploaded here:

    http://img707.imageshack.us/img707/2150/appuntiwindows1c.jpg

     

     

  • 0 in reply to Mark81
    TI__Mastermind 43915 points

    Hi Marco,

    The digital supplies IOVDD and DVDD need to come up before the high voltage supplies. Otherwise, the OTP will not be written correctly causing the DAC to power up in unipolar mode regardless of their being two high voltage supplies. Looks like you have IOVDD and DVDD tied together to 3.3V. You just need to make sure that the 3.3V comes up before the +/-12V high voltage supplies. This is required in order to get the part to work properly.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Expert 2610 points

    Tony,

    I fixed the issue adding a small RC network on the DCDC input. Now the ±12V comes up after 3.3V and REFx comes up last. In fact, now it works fine. What is the best way to tget proper sequencing you recommend? I think the RC delay is not a good solution...

  • 0 in reply to Mark81
    TI__Mastermind 43915 points

    Hi Marco,

    I agree that using a RC is not the best solution. Previous customers that do not have control over their power supply sequencing were forced to use external power conditioning circuitry to ensure that the device powers up correctly. Some customers have gone the route of a bulk capacitor on the high voltage supplies to try and slow the ramp time but that is a very high risk solution when going into production of boards.

    Regards,

    Tony

  • 0 in reply to Tony Calabria
    Expert 2610 points

    Tony,

    I have the last question for you. Reading the datasheet at page 44, it says:

    "For proper power-on initialization of the device, IOVdd and the digital pins must be applied before or at the same time as DVdd"

    well, but the Absolute Maximum Ratings table states:

    "IOVDD to DGND –0.3 to min of (6 or DVDD + 0.3) V"

    I wonder how it is possible to raise IOVdd before DVdd without exceed this constraint.

  • 0 in reply to Mark81
    TI__Mastermind 43915 points

    Hi Marco,

    There is an internal diode between the IOVdd and DVdd line to ensure that the DVdd line is greater than or within 300mV of IOVdd. Generally customers have tied the DVDD and IOVDD lines together during power up or use the DVDD line to generate the IOVdd via a regulator to have them come up relatively at the same time. If IOVdd is brought high well before DVdd, you will forward bias that internal diode and cause the IOVdd line to draw slightly more current to power DVdd. Once the DVdd power comes high, the current draw from IOVdd will return to its expected value. How long of a period do you expect between the IOVdd and DVdd lines coming high?

    Regards,

    Tony Calabria.

  • 0 in reply to Tony Calabria
    Expert 2610 points

    Tony,

    it was just to understand the datasheet. In my design DVdd and IOVdd are tied together so there is no problem on this topic. I thank you again for you answers. I was able to fix my circuit and to understand how to use the component.