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ADS5474 digital correction principles

Sergey Zadvornov
Prodigy 20 points
Other Parts Discussed in Thread: ADS5474

Hello,

I'm using this A/D converter (ADS5474) integrated in the data acquisition board. According to ADS5474 datasheet three data lines of 5 , 5 and 6 bits  (16 bits totally) are processed in  digital error correction circuit. For my calibration purposes, may I have any general idea of how this correction works? First of all, two MSBs are finally ignored, two LSBs or "one LSB and one MSB" to have 14bit-wide data line at the end?

 

Thank you.

 

  • 0
    TI__Mastermind 29220 points

    Hi,

    Actually, there is a bit of overlap between the pipeline stages.  There are not any bits that are discarded at either end, really.  Rather - the first stage provides 5 bits of resolution, the second stage of 5-bits provides an additional 4 bits of resolution, and the final stage of 6 bits provides an additional 5 bits of resolution.  During the manufacture and test process, there are fuse trim bits that are set to trim out gain and offset mismatches between the pipeline stages, and the extra overlap bits are needed for that process.  But the final (trimmed) output is still only 14 unique bits.

     

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 20 points

    Hello Richard,

    Thank you for your explication. But does the formula for this transformation exist? Is it possible to know more about it for this 14-bit ADC?

    It is known, for example, that for some 12-bit ADCs having three stages a, b, c (4, 4 and 5 bits each) their redundant (!) code may be represented by formula:

    D = 24*(12*a + b) + c

     

    How it works for ADS5474 ?

     

    Regards,

    Sergey

     

  • 0 in reply to Sergey Zadvornov
    TI__Mastermind 29220 points

     

    This is the explanation I get from the lead designer for this device.

    Regards,

    Richard P.